Floating Gate Barrier Thickness Asymmetry for Leakage Control
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Solution Overview
Problem
The miniaturization and integration of nonvolatile memory devices lead to increased aspect ratios of floating gates, concentrating electric fields and affecting the reliability and operation of the devices, resulting in issues with leakage current and reduced performance.
Innovation Solution
The implementation of a nonvolatile memory device design featuring a floating gate with a lower barrier layer having a thicker first layer on the upper surface and a thinner second layer on the side surface, along with an inter-gate dielectric layer and a control gate, helps mitigate electric field concentration by varying the thickness of the barrier layers and dielectric layers to improve reliability and operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the floating gate is miniaturized and integrated to increase aspect ratio, then device integration density is improved, but electric field concentration increases causing reliability degradation
Solution Approach 1:
The patent applies local quality by creating a non-uniform barrier layer structure where the thickness varies at different locations. Specifically, the barrier layer has a first thickness at the upper surface of the floating gate and a second thickness at the side surface, with the first thickness being greater than the second thickness. This local variation in barrier layer thickness allows different regions to serve different functions: the thicker upper portion mitigates electric field concentration at the critical upper region, while the thinner side portion maintains proper device operation and integration.
2Reliability
If the barrier layer thickness is increased to reduce electric field concentration, then reliability is improved, but device dimensions increase affecting miniaturization
Solution Approach 1:
The barrier layer is designed with locally differentiated thickness to optimize reliability without excessive overall dimension increase. The first barrier layer at the upper surface has a greater thickness to specifically address electric field concentration, while the second barrier layer at the side surface has a smaller thickness. This localized thickening only where needed (at the upper surface) rather than uniformly increasing all barrier layer dimensions allows reliability improvement while maintaining device miniaturization.
Solution Approach 2:
The patent employs asymmetry by creating an asymmetric barrier layer structure where the thickness distribution is non-uniform. The barrier layer thickness is asymmetric with respect to the floating gate, being thicker at the upper surface and thinner at the side surface. This asymmetric design optimizes the electrical field distribution by providing enhanced protection where the field concentration is most problematic (upper surface) while avoiding unnecessary material and space consumption in other regions.
Data Source
AI summary
Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.