Floating Gate Buffer Layer for Void-Free STI and CMP Uniformity
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Solution Overview
Problem
Conventional semiconductor manufacturing methods face challenges in simultaneously preventing voids in shallow trench isolation and floating gates, and suffer from loading effects during the CMP process, making it difficult to achieve optimal device performance.
Innovation Solution
The method involves forming a first and second hard mask layer over a semiconductor substrate, creating trenches, and filling them with dielectric material to form shallow trench isolation regions. A buffer layer is repeatedly deposited and polished over the floating gate material, with a dry etch process used to remove portions above the shallow trench isolation regions, ensuring the buffer and floating gate surfaces are coplanar, and maintaining the desired thickness and morphology of the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of silicon nitride layer is increased to 1.5-2 times the final floating gate thickness, then the floating gate can be properly formed, but the aspect ratio in the filler dielectric material becomes high leading to cavity formation in shallow trench isolation
Solution Approach 1:
The patent applies preliminary action by forming a buffer layer over the floating gate material before performing CMP. This buffer layer is deposited in advance to prevent direct contact between the CMP slurry and the floating gate material, thereby preventing cavities in the shallow trench isolation while still allowing proper floating gate formation. The buffer layer serves as a protective intermediary that resolves the contradiction between maintaining floating gate thickness and preventing STI voids.
Solution Approach 2:
The buffer layer acts as an intermediary between the CMP process and the floating gate material. By introducing this intermediate layer, the patent enables the CMP process to proceed without directly exposing the floating gate material to the slurry, thus preventing cavity formation in the shallow trench isolation while maintaining the integrity of the floating gate structure.
2Measurement precision
If self-aligned method is used to form floating gate material layer, then alignment precision is improved, but small size active area regions lead to voids within the floating gate
Solution Approach 1:
The buffer layer is formed preliminarily over the floating gate material before CMP. This preliminary protective layer prevents the CMP slurry from directly contacting and creating voids in small active area regions, while still allowing the self-aligned method to maintain its alignment precision benefits.
3Shape
If CMP process is used to planarize floating gate layer, then surface flatness is improved, but loading effects cause floating gate thickness loss in pad area
Solution Approach 1:
The buffer layer serves as an intermediary protective layer during CMP. It absorbs the mechanical and chemical effects of the CMP slurry, preventing direct erosion of the floating gate material. This intermediary layer maintains surface flatness through CMP while preventing the loading effects that cause thickness loss in pad areas.
Solution Approach 2:
The buffer layer provides beforehand cushioning by being deposited over the floating gate material prior to CMP. This protective layer cushions the floating gate material against the harsh CMP environment, preventing excessive thickness removal and maintaining thickness uniformity across different regions including pad areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces void formation in both shallow trench isolation and floating gates, improves the floating gate's thickness and morphology, and mitigates the loading effects during the CMP process, resulting in enhanced semiconductor device performance.
Implementation Method 1
perform CMP (chemical mechanical polish) to form a shallow trench isolation (STI)
Implementation Method 2
a dry etch process to remove a portion of the floating gate material above the shallow trench isolation regions
Data Source
AI summary
A method for forming a semiconductor device includes forming first and second hard mask layers overlying a semiconductor substrate and forming trenches through the second hard mask, the first hard mask, and into the substrate. A dielectric material is formed in the trenches to form shallow trench isolation regions, removing the second hard mask layer, and a floating gate material is formed overlying the first hard mask and the trenches. The method further includes repeating at least twice a process of forming a buffer layer over the floating gate material and using a polishing process to remove a portion of the buffer layer and a top portion of the floating gate material. Next, a dry etch process to remove a portion of the floating gate material above the shallow trench isolation regions and the remaining portions of the buffer layer to form floating gate structures.