Floating-Gate Memory Cell Structure for Independent Byte Erase
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Solution Overview
Problem
Conventional non-volatile memory devices lack the ability to perform independent byte-level programming and erasing operations without affecting other memory cells sharing the same word lines, which limits their flexibility in memory applications.
Innovation Solution
The design incorporates a non-volatile memory device structure with an assist gate, a byte select gate, a floating gate, and an upper gate, along with independent erase and select gate lines, allowing for independent programming and erasing of each byte by embedding the upper edge of the floating gate within the upper gate and spacing the byte select gate apart, enabling independent control of each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional stack-gate structure with shared word lines is used, then the device complexity is reduced and manufacturing is easier, but the ability to perform independent byte-level programming and erasing operations is lost
Solution Approach 1:
The gate structure is segmented into multiple independently controllable gates: assist gate, byte select gate, floating gate, and upper gate. Each gate can be controlled independently through separate gate lines, enabling selective programming and erasing of specific bytes while leaving other bytes unaffected. This segmentation directly enables byte-level independent operation capability.
Solution Approach 2:
The patent introduces a new vertical dimension by stacking multiple gates (assist gate, floating gate, upper gate) in the vertical direction rather than using a simple planar structure. This three-dimensional gate arrangement allows for more complex control logic and enables independent byte operations by applying voltages to specific gate combinations.
2Productivity
If electrons are injected into or pulled out of the floating gate through the tunneling oxide layer during programming or erase operations, then the gate-coupling ratio is improved and operating speed increases, but the tunneling oxide layer structure is damaged and reliability reduces
Solution Approach 1:
The upper gate acts as an intermediary structure that enables electron transfer without directly stressing the tunneling oxide layer. By applying voltages to the upper gate in combination with the assist gate and byte select gate, electrons can be injected into or extracted from the floating gate through field effect and tunneling mechanisms that are less damaging to the oxide layer structure.
Solution Approach 2:
The patent changes the voltage parameters applied to different gates during programming and erasing operations. By carefully controlling the voltage combinations on the assist gate, byte select gate, and upper gate, the electric field distribution is optimized to enable efficient electron transfer while reducing stress on the tunneling oxide layer, thus maintaining both operating speed and reliability.
3Reliability
If an erase gate is added to pull electrons from the floating gate through the tunneling oxide layer on the floating gate, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The upper gate serves multiple functions: it acts as an erase gate for extracting electrons from the floating gate, a control gate for programming operations, and a means for enabling byte-level selection. This multi-functionality reduces the need for separate dedicated erase gates, thereby limiting the increase in device complexity while still improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for independent programming and erasing of each byte, enhancing the memory device's reliability and operational flexibility by reducing the stress on the tunneling oxide layer and enabling sector or individual byte operations without disturbing other memory cells.
Implementation Method 1
When a programming or erasing operation is performed on such a flash memory device, a suitable voltage is respectively applied to the source region, the drain region, and the control gate, such that electrons are injected into a floating gate, or electrons are pulled out from the floating gate
Implementation Method 2
the assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region
Data Source
AI summary
A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.