Floating Gate Cap Charge Trapping for Leakage Current Reduction
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Solution Overview
Problem
Non-volatile semiconductor memory devices face increased leakage current due to electric field concentration at the top of the floating gate, leading to data retention issues.
Innovation Solution
A floating gate cap with a charge trap site is introduced between the floating gate and the gate dielectric pattern, reducing electric field concentration and leakage current by localizing charges, and the gate dielectric layer is made thicker on the top surface than on the sidewalls to further mitigate this effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional floating gate structure is used, then the device structure is simple, but leakage current increases due to electric field concentration at the top of the floating gate
Solution Approach 1:
A gate dielectric layer is introduced as an intermediary between the floating gate and the control gate. This intermediate layer prevents direct electric field coupling at the top corner of the floating gate, thereby reducing leakage current while maintaining the overall simplicity of the device structure
Solution Approach 2:
The gate dielectric layer is positioned specifically at the top corner region of the floating gate where electric field concentration occurs. This localized modification addresses the leakage problem at the critical area without requiring changes to the entire device structure
2Reliability
If the gate dielectric layer is made uniformly thick, then the manufacturing process is simple, but leakage current persists due to electric field concentration at the top of the floating gate
Solution Approach 1:
The gate dielectric layer is formed with non-uniform thickness, being thicker at the top surface of the floating gate and thinner at the sidewalls. This localized thickness variation directly addresses the electric field concentration at the top corner, reducing leakage current while the thickness gradient is achieved through controlled deposition processes
Solution Approach 2:
The thickness parameter of the gate dielectric layer is varied spatially across the floating gate structure. By changing the thickness from the top surface to the sidewalls, the electric field distribution is modified to reduce concentration effects and leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and improves data retention by localizing charges in the floating gate cap, thereby enhancing the endurance of non-volatile memory devices.
Implementation Method 1
a floating gate cap with a charge trap site is introduced between the floating gate and the gate dielectric pattern, reducing electric field concentration and leakage current by localizing charges
Implementation Method 2
the gate dielectric layer is made thicker on the top surface than on the sidewalls to further mitigate this effect
Data Source
AI summary
Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.