Floating Gate Layout for Lower Contact Resistance in Flash Memory
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Solution Overview
Problem
Existing flash memory devices face issues with high contact resistance and non-uniformity of contact structures due to high aspect ratio contact structures, leading to reduced yield, reliability, and data retention ability.
Innovation Solution
The solution involves forming non-volatile memory devices with a substrate having a center region and border regions, where the border regions have second floating gates with a smaller width and greater spacing compared to the first floating gates in the center region, improving the uniformity and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the spacing between gate structures is increased to reduce contact resistance, then contact resistance decreases, but the width of gate structures must be reduced which causes data retention ability to decrease and operation time to increase
Solution Approach 1:
The patent applies local quality by differentiating the array region into center and border regions with different gate structure configurations. Border region gate structures have larger spacing and larger width compared to center region, allowing optimized contact resistance in border areas without compromising the data retention and operation time of the center region memory cells.
2Manufacturing precision
If the width of gate structures is reduced to increase spacing, then spacing increases and contact resistance decreases, but data retention ability is reduced
Solution Approach 1:
The patent implements local quality by creating region-specific gate structures: center region gate structures maintain smaller width for high density and good data retention, while border region gate structures use larger width and spacing to achieve uniform contact structures and reduced contact resistance, thus resolving the uniformity issue without sacrificing data retention in the main array.
3Manufacturing precision
If the spacing between gate structures is increased to improve uniformity, then uniformity of contact structures improves, but the width of gate structures must be reduced causing reduced data retention ability
Solution Approach 1:
The patent applies local quality by configuring border region gate structures with larger spacing and larger width compared to center region. This local differentiation achieves uniform contact structures in the border region (improving manufacturing precision) while preserving the optimized center region configuration that ensures data retention reliability.
4Ease of manufacture
If gate structures in border regions have the same dimensions as center region, then manufacturing is simpler, but contact resistance becomes non-uniform and yield decreases
Solution Approach 1:
The patent implements local quality by introducing different gate structure dimensions for border regions compared to center region. Although this increases manufacturing complexity slightly, it achieves uniform contact structures across the array and reduces contact resistance, thereby improving yield and overall device reliability.
Solution Approach 2:
The patent applies asymmetry by creating non-uniform gate structure configurations across the array - border region gate structures have different (larger) spacing and width compared to center region gate structures. This asymmetric design compensates for edge effects and ensures uniform electrical characteristics throughout the array, improving yield.
Data Source
AI summary
A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a substrate and a plurality of first floating gates and a plurality of second floating gates formed on the substrate. The substrate includes a center region and two border regions located on opposite sides of the center region. The center region and two border regions are located in an array region. The first floating gates are located in the center region, and the second floating gates are located in one of the border regions. Each of the first floating gates has a first width, and each of the second floating gates has a second width less than the first width. There is a first spacing between the first floating gates, and there is a second spacing which is greater than the first spacing between the second floating gates.