Floating Gate Memory Structure to Prevent Tunnel Oxide Corner Thinning
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Solution Overview
Problem
The continuous scaling down of semiconductor devices leads to increased susceptibility to defects, such as corner thinning of the tunnel oxide layer, which adversely affects memory performance.
Innovation Solution
A method for forming a semiconductor structure that includes providing a semiconductor substrate with a tunnel dielectric layer, a conductive layer, and a mask layer, followed by etching to define stack structures and trenches. A liner is formed on the sidewalls of the stack structures to protect the tunnel dielectric layer, and an isolation structure is formed in the trenches. The process continues with forming a floating gate, recessing the isolation structure, and depositing an inter-gate dielectric layer and a control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of non-volatile memory is continuously reduced to increase integration, then device integration is improved, but corner thinning of the tunnel oxide layer occurs which degrades memory performance
Solution Approach 1:
A liner layer is formed on the sidewalls of the stack structure before the etching process. This preliminary protective layer prevents corner thinning of the tunnel oxide layer during subsequent etching operations, allowing continuous scaling while maintaining layer integrity and uniformity
Solution Approach 2:
The liner layer acts as an intermediary protective barrier between the etching process and the tunnel oxide layer. It absorbs the mechanical stress and protective function during etching, preventing direct damage to the tunnel oxide layer corners while enabling continued device scaling
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a tunnel dielectric layer, a conductive layer and a hard mask layer; etching the semiconductor layer, the tunnel dielectric layer, the conductive layer and the hard mask layer to define stack structures and trenches; forming a liner on the sidewalls of the stack structures; forming an isolation structure in the trenches; removing the hard mask layer to form openings exposing the conductive layer; filling the openings with a conductive material to form a floating gate which includes a lower portion covered by the liner and an upper portion not covered by the liner; recessing the isolation structure to expose the sidewalls of the upper portion of the floating gate; forming an inter-gate dielectric (IGD) layer on the isolation structure and the floating gate; and forming a control gate on the IGD layer.