Floating Gate Memory Coupling Compensation via Multi-Stage Verification
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Solution Overview
Problem
The challenge in non-volatile semiconductor memory, particularly in multi-state flash memory devices, is the floating gate to floating gate coupling that leads to erroneous readings due to shifts in apparent charge storage, exacerbated by shrinking memory cell sizes and increased coupling between adjacent cells.
Innovation Solution
A method involving coarse and fine verification levels during programming to reduce coupling between adjacent floating gates, where subsets of non-volatile storage elements are programmed using specific target levels and verification processes managed by a circuitry system, including control lines and a managing circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase storage density, then storage capacity is improved, but coupling between adjacent floating gates increases causing erroneous readings
Solution Approach 1:
The patent segments the programming process into multiple phases with different verification levels. During programming, different word lines are programmed to different target threshold voltages in a controlled sequence, and verification is performed at multiple stages to detect and correct coupling-induced threshold voltage shifts before they cause erroneous data storage.
Solution Approach 2:
The patent performs preliminary verification during the programming process itself, rather than only after completion. By implementing verification at multiple stages (during programming and after programming), the system can detect threshold voltage shifts caused by coupling effects before they result in incorrect data, allowing for corrective action to be taken.
2Reliability
If multiple verification levels are used during programming to reduce coupling effects, then reading accuracy is improved, but programming complexity increases
Solution Approach 1:
The patent changes the verification parameter (threshold voltage level) at different stages of programming. Multiple verification levels are used corresponding to different target threshold voltages for different word lines. This allows the system to adaptively verify programming status at appropriate voltage thresholds, reducing coupling effects while managing complexity through systematic parameter variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the impact of floating gate coupling, ensuring accurate data storage and retrieval by maintaining precise threshold voltage distributions across memory cells, even as cell sizes decrease and coupling effects increase.
Implementation Method 1
The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Implementation Method 2
Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state.
Implementation Method 3
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the change stored in adjacent floating gates.
Data Source
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AI summary
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).