Floating-Gate Memory Structure for Higher Coupling and Oxide Endurance
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Solution Overview
Problem
Conventional flash memory devices face limitations in reducing device size due to reduced channel length and coupling ratio between the floating gate and control gate, leading to increased operating voltage and reduced endurance of the tunnel oxide layer.
Innovation Solution
A semiconductor memory device with dual channel regions of different doping concentrations and spacer-type floating gates with curved sidewalls, separated by a semiconductor layer, enhances the coupling rate between the floating and control gates, and avoids electrical short circuits during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced, then integration density is improved, but coupling ratio between floating gate and control gate deteriorates
Solution Approach 1:
The patent introduces a third vertical dimension by stacking the control gate above the floating gate, transforming the conventional planar two-dimensional layout into a three-dimensional vertical structure. This dimensional change increases the coupling capacitance between gates without increasing planar footprint, thereby maintaining high coupling ratio while achieving high integration density.
Solution Approach 2:
The control gate is positioned directly above and nested over the floating gate, creating a stacked configuration where one gate structure contains another in the vertical dimension. This nesting arrangement maximizes the overlapping area between gates, enhancing coupling ratio while minimizing lateral space consumption for higher integration density.
2Quantity of substance
If device size is reduced, then integration density is improved, but operating voltage increases
Solution Approach 1:
By transitioning to a vertical stacked architecture, the patent achieves stronger electric field coupling between gates in the vertical dimension, which improves charge transfer efficiency. This reduces the voltage required for write and erase operations, thereby lowering operating voltage while maintaining high integration density.
Solution Approach 2:
The patent modifies the geometric parameters of the gate structures, including reducing gate lengths and optimizing overlapping areas in the vertical stack. These parameter changes enhance the electric field efficiency, allowing effective operation at reduced voltage levels while preserving integration density.
3Device complexity
If single channel region is used for write and erase operations, then device structure is simplified, but tunnel oxide layer endurance deteriorates
Solution Approach 1:
The patent divides the channel region into two distinct segments: a first channel region for write operations and a second channel region for erase operations. This segmentation allows the tunnel oxide layer to be selectively stressed during operations, enabling recovery periods that extend the overall endurance of the oxide layer while maintaining relatively simple device structure.
Solution Approach 2:
Different regions of the channel are assigned different doping concentrations and functional roles - the first channel region is optimized for write operations with appropriate doping, while the second channel region is optimized for erase operations. This local differentiation protects the tunnel oxide layer from cumulative damage by distributing stress across different regions, extending endurance without significantly increasing device complexity.
4Ease of manufacture
If source/drain regions are located on the same plane as channel region, then manufacturing is simplified, but channel length control is restricted
Solution Approach 1:
The patent positions source and drain regions in different vertical planes relative to the channel region, creating a three-dimensional arrangement. This vertical separation allows independent optimization of channel length without being constrained by planar geometry, enabling better channel length control while maintaining manufacturing feasibility through adapted fabrication processes.
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes a semiconductor substrate and transistor structures. The transistor structures are disposed on the semiconductor substrate. Each of the transistor structures includes a semiconductor layer, a floating gate, a control gate, a tunneling oxide layer, and an inter-gate dielectric layer. The semiconductor substrate and the semiconductor layer have the same conductivity type and different doping concentrations. The floating gate covers a sidewall of the semiconductor layer and has a curved sidewall opposite the sidewall of the semiconductor layer. The tunneling oxide layer is between the floating gate and the semiconductor substrate and between the first floating gate and the semiconductor layer. A control gate is disposed on the floating gate and an inter-gate dielectric layer is between the control gate and the floating gate and conformally covers the curved sidewall of the first floating gate.