Floating-Gate Memory Structure for Higher Coupling Ratio
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Solution Overview
Problem
The efficiency of programming and erasing operations in flash memory cells is limited by the coupling ratio between the control gate and the floating gate, which is constrained by the capacitance ratio of the gate dielectric and interlevel dielectric layers, necessitating an enhancement of the control gate-floating gate capacitance to improve operational efficiency.
Innovation Solution
The method involves forming gate stacks with specific configurations, including openings and separate portions, to increase the surface area of the dielectric layer between the floating gate and control gate electrodes, thereby enhancing the control gate-floating gate capacitance and coupling ratio, and using a dielectric film with an ONO structure to reduce junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric and interlevel dielectric layer thicknesses are reduced to increase coupling ratio, then the coupling ratio improves, but junction leakage increases
Solution Approach 1:
The patent implements a nested dielectric structure where an inner dielectric layer (first dielectric material) is positioned between the floating gate and control gate, surrounded by an outer dielectric layer (second dielectric material). This nested configuration allows the inner layer to provide high-k insulation that reduces junction leakage, while the outer layer maintains the overall capacitance coupling ratio, thus resolving the contradiction between improving coupling ratio and preventing leakage.
Solution Approach 2:
The patent employs composite dielectric materials with different properties - a first dielectric material with higher dielectric constant positioned adjacent to the floating gate to reduce leakage, and a second dielectric material forming the interlevel dielectric layer. This composite structure enables simultaneous optimization of coupling ratio and leakage reduction by leveraging the complementary properties of different materials.
2Productivity
If the control gate-floating gate capacitance is increased to improve programming efficiency, then the coupling ratio improves, but the device complexity increases
Solution Approach 1:
The patent enhances capacitance coupling not by increasing lateral dimensions but by utilizing the vertical dimension - positioning the high-k inner dielectric layer in the vertical stack between floating gate and control gate. This dimensional approach increases capacitance (improving programming efficiency) without expanding the lateral footprint, thus avoiding increased device complexity.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the material between floating gate and control gate by introducing a high-k inner dielectric layer. This parameter change directly increases the capacitance coupling ratio and programming efficiency without requiring additional structural elements, thereby avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the coupling ratio, reduces leakage currents, and improves data retention by increasing the control gate-floating gate capacitance and minimizing drain disturb, leading to more efficient programming and erasing operations.
Implementation Method 1
a dielectric layer over the floating gate electrode. The control gate electrode is in contact with the dielectric layer
Data Source
AI summary
A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.