Floating Gate Sidewall Structure for Higher Flash Memory Coupling
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Solution Overview
Problem
Current flash memory devices face challenges in achieving optimal coupling ratios and performance due to limitations in floating gate design, particularly with polysilicon gates, which affect data retention and programming speed.
Innovation Solution
The manufacturing process involves forming a floating gate with a concave sidewall and a specific dielectric structure, including a control gate, spacer structures, and an erase gate, to enhance coupling ratios without thinning the dielectric layer or increasing the floating gate thickness, thereby improving memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer is thinned or floating gate thickness is increased to improve coupling ratio, then coupling ratio between floating gate and erase gate is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The floating gate is formed with a concave sidewall profile instead of a straight vertical sidewall. This curvature in the sidewall geometry increases the surface area of the floating gate that faces the erase gate, thereby enhancing the coupling ratio between these two gates without requiring changes to the dielectric layer thickness or floating gate material composition.
Solution Approach 2:
The invention transitions from a two-dimensional view of gate coupling (considering only horizontal spacing and vertical thickness) to a three-dimensional solution by modifying the sidewall profile. The concave sidewall introduces a geometric dimension that allows the floating gate to extend closer to the erase gate in the vertical direction while maintaining appropriate horizontal spacing, thus improving coupling without compromising manufacturing feasibility.
2Productivity
If memory array density is increased through aggressive scaling, then memory capacity and performance are improved, but maintaining efficient coupling ratios becomes more difficult
Solution Approach 1:
As memory features are scaled down to increase array density, the concave sidewall profile becomes increasingly effective. The curved geometry allows the floating gate to maintain a larger effective coupling area with the erase gate even when overall dimensions are reduced, thereby preserving coupling ratios despite aggressive scaling.
Solution Approach 2:
The concave sidewall configuration creates a localized enhancement of the floating gate structure specifically at the region facing the erase gate. This local geometric modification concentrates the coupling effect where it is most needed, allowing the rest of the structure to be scaled down more aggressively to increase density while maintaining coupling performance in the critical interface region.
Data Source
AI summary
A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.