Floating Gate With Dielectric Islands For Charge Trapping
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Solution Overview
Problem
As device size decreases in flash memory devices, the ability to store charge also decreases due to the smaller size of the floating gate, necessitating alternative memory device structures and methods to enhance charge trapping capabilities.
Innovation Solution
The introduction of a floating-gate memory cell with a conductive continuous component and a discontinuous dielectric component, which increases charge trapping sites by providing additional surface area for charge storage while maintaining bulk conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the floating gate size is decreased to reduce device size, then device miniaturization is achieved, but the charge storage capacity decreases
Solution Approach 1:
The patent introduces a discontinuous dielectric component within the floating gate structure that creates additional dimensional complexity. This dielectric component forms islands or regions that increase the effective surface area for charge trapping without increasing the overall device footprint, thereby enabling enhanced charge storage capacity in a miniaturized device structure.
Solution Approach 2:
The floating gate is constructed as a composite structure combining conductive material with a discontinuous dielectric component. This composite architecture allows the conductive portion to maintain electrical functionality while the dielectric portions provide additional charge trapping sites, effectively increasing charge storage capacity without proportionally increasing device size.
2Length of moving object
If the floating gate thickness is reduced to enable miniaturization, then device scaling is achieved, but the charge trapping capability decreases
Solution Approach 1:
By incorporating a discontinuous dielectric component with vertical and lateral extensions within the floating gate, the patent creates additional trapping surfaces in multiple dimensions. This allows charge trapping capability to be enhanced without increasing the overall thickness of the floating gate, as the dielectric structures provide internal surface area for charge storage.
Solution Approach 2:
The discontinuous dielectric component creates a porous or multi-region structure within the floating gate. These dielectric islands or regions provide numerous internal surfaces and interfaces that serve as charge trapping sites, effectively increasing charge trapping capability without requiring increased gate thickness.
3Productivity
If the floating gate size is decreased to improve integration density, then manufacturing capacity increases, but the charge storage per cell decreases
Solution Approach 1:
The composite floating gate structure combining conductive and dielectric materials enables enhanced charge storage density within each miniaturized cell. The dielectric component provides additional charge trapping sites that compensate for the reduced cell size, maintaining charge storage per cell while improving overall integration density across the memory device.
Solution Approach 2:
The discontinuous dielectric component adds structural complexity in multiple dimensions within the floating gate, creating additional charge trapping surfaces without increasing the lateral or vertical footprint of the memory cell. This enables higher integration density while preserving charge storage capacity per cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge carrier storage capacity and retention, allowing for reduced floating gate thickness and improved coupling ratios between the floating and control gates, enabling further miniaturization and efficient data storage.
Implementation Method 1
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate
Implementation Method 2
The conductive portion includes a continuous component providing bulk conductivity to the floating gate
Data Source
AI summary
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.