Floating Gate Doping Region for Flash Memory Write Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory structures, particularly flash memory, face challenges in write and erase operations due to damage from hot electrons accumulating near the interface between the floating gate and tunnel dielectric layer, leading to data loss and instability in operating voltage.
Innovation Solution
A memory structure with a doping region buried in the lower portion of the floating gate, where the sidewall of the doping region is exposed and separated from the inter-gate dielectric layer, enhances the write operation by applying a lateral force to hot electrons, reducing damage to the tunnel dielectric layer and maintaining stable capacitance with the control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hot electrons are used for write operation in flash memory, then programming speed is improved, but tunnel dielectric layer is damaged due to electron accumulation
Solution Approach 1:
The patent converts the harmful accumulation of hot electrons near the tunnel dielectric interface into a beneficial effect by introducing a doping region that creates a lateral force. This lateral force redirects the hot electrons away from the tunnel dielectric layer, preventing damage while maintaining the high-speed programming capability. The harmful electron accumulation is transformed into a controlled current path that benefits the write operation.
Solution Approach 2:
The patent applies local quality by creating a doping region with specific electrical properties (different conductivity type) localized in the lower portion of the floating gate. This localized doped region generates an electric field that exerts lateral force only in the critical area near the tunnel dielectric interface, where hot electron damage occurs. The rest of the floating gate maintains its original properties for normal operation.
2Productivity
If higher voltage is applied to accelerate write operation, then programming speed is improved, but damage to tunnel dielectric layer increases
Solution Approach 1:
The patent changes the electrical parameter distribution within the floating gate by introducing a doping region. This creates a lateral electric field component that alters the trajectory of hot electrons. Instead of increasing voltage to improve speed (which would increase damage), the patent modifies the field distribution parameters to achieve both high speed and low damage simultaneously.
Solution Approach 2:
The doping region acts as an intermediary element between the hot electrons and the tunnel dielectric layer. It mediates the interaction by generating a lateral force that redirects electrons away from the dielectric layer, preventing direct harmful contact while still utilizing the hot electron mechanism for fast programming.
3Productivity
If doping region is added to floating gate, then write operation is improved, but device complexity increases
Solution Approach 1:
The patent segments the floating gate into different functional regions: a doped lower portion that generates lateral force to protect the tunnel dielectric, and an undoped upper portion that maintains normal floating gate functionality. This segmentation allows each region to perform its specific function optimally while keeping the overall structure manageable.
Solution Approach 2:
The doping region is formed in advance during the manufacturing process, before the memory operates. This preliminary action of creating the doped region establishes the protective lateral force mechanism beforehand, so that during normal high-speed write operations, the protection is already in place without requiring additional complex control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design accelerates write operation speed, reduces the required voltage, and prevents tunnel dielectric layer damage, ensuring reliable data storage and improved memory structure reliability.
Implementation Method 1
enhances the write operation by applying a lateral force to hot electrons
Implementation Method 2
hot electrons accumulating near the interface between the floating gate and tunnel dielectric layer
Data Source
AI summary
A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.