Floating Gate Carbon Doping Gradient for Etching Damage Reduction
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Solution Overview
Problem
Existing methods for manufacturing NAND devices face challenges in protecting the middle and lower portions of the floating gate polysilicon from damage during etching, despite the bottom portion being stable due to carbon doping.
Innovation Solution
A method involving a floating gate with a thickness greater than 400 Å, divided into regions, where the bottom portion is carbon doped with gradually decreasing flow rates from 200 sccm to 50 sccm, and the upper portion is not doped, followed by the formation of a stack layer and control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If carbon doping is applied uniformly to the entire floating gate, then the bottom portion stability is improved, but the middle and lower portions still suffer damage during etching
Solution Approach 1:
The patent applies carbon doping with gradually decreasing flow rates to different regions of the floating gate. The first region (bottom 200-400 Å) receives higher carbon doping concentration while the second region (upper portion) receives lower or no carbon doping, creating a gradient structure that provides localized protection where needed most during etching processes
2Strength
If the floating gate thickness is increased to improve stability, then etching damage resistance is improved, but the complexity of the deposition process increases
Solution Approach 1:
The patent changes the carbon doping flow rate parameter during deposition, transitioning from higher flow rates (200 sccm) for the bottom region to lower flow rates (50 sccm) for the upper region. This parameter variation creates a hardness gradient within the floating gate, providing enhanced protection at the vulnerable bottom portion while maintaining overall process feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the hardness and stability of the floating gate polysilicon, reducing damage during etching and improving the reliability of NAND devices.
Implementation Method 1
the floating gate is doped with carbon at the bottom 200 Å region during deposition to increase the hardness of the floating gate
Implementation Method 2
forming a floating gate on the tunneling oxide layer... performed carbon doping deposition to the first region of the floating gate
Data Source
AI summary
The present disclosure provides a method of reducing damage to floating gate polysilicon during etching. The method includes: forming a floating gate thicker than 400 Å on a tunneling oxide layer, forming a first region including a portion of the floating gate from the bottom to the 400 Å thickness, and forming a second region including a portion of the floating gate above the 400 Å thickness; performing carbon-doping deposition into the first region of the floating gate, wherein a carbon doping process is arranged to be in gradually decreasing flow rate in a direction from the bottom of the floating gate up to the 400 Å thickness, and the second region is not subjected to carbon doping; forming a stack layer including silicon oxide, silicon nitride, and silicon oxide on the floating gate; and forming a control gate on the stack layer.