Floating Gate Area Reduction for EPROM Fuse Replacement
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Solution Overview
Problem
Inkjet printheads using NMOS chips with fuse technology face issues of unreliable fuses that can damage the orifice layer and cause ink blockages, leading to poor printing quality.
Innovation Solution
The use of electronically programmable read-only memory (EPROM) devices with a floating gate structure, which includes a semiconductor substrate, a floating gate, and a control gate capacitively coupled via dielectric material, allowing for programming via hot carrier injection to change the threshold voltage and logic state without physical alteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuse technology is used in NMOS chips for programming, then a bit can be programmed by selectively burning fuses, but the fuses are relatively large and unreliable and can damage the orifice layer during programming
Solution Approach 1:
The patent replaces the mechanical fuse-burning process with an electronic programming mechanism using EPROM cells. Instead of physically burning fuses to program bits, the invention uses electric field effects to trap or release electrons in the floating gate, thereby programming the memory cell electronically without mechanical damage.
Solution Approach 2:
The invention extracts and eliminates the fuse component entirely from the system. By using EPROM memory cells with floating gates, the design removes the need for separate fuse elements, thereby eliminating the reliability issues and damage risks associated with fuse burning while maintaining programming functionality.
2Ease of manufacture
If fuses are burned to program bits, then programming can be achieved, but metal debris from the fuse can be drawn into the ink and cause blockage in the inkjet pen
Solution Approach 1:
The patent replaces the mechanical fuse-burning process with an electronic programming mechanism using EPROM cells. Instead of physically burning fuses to program bits, the invention uses electric field effects to trap or release electrons in the floating gate, thereby programming the memory cell electronically without mechanical damage.
Solution Approach 2:
The invention extracts and eliminates the fuse component entirely from the system. By using EPROM memory cells with floating gates, the design removes the need for separate fuse elements, thereby eliminating the reliability issues and damage risks associated with fuse burning while maintaining programming functionality.
3Reliability
If the active floating gate width is reduced to improve EPROM performance, then control gate capacitance to floating gate capacitance ratio increases, but the floating gate area decreases
Solution Approach 1:
The patent applies local quality by creating different width regions within the floating gate structure. The floating gate has a narrower active region under the channel where electron trapping occurs, and wider regions at the ends for electrical connection. This localized narrowing increases the control gate to floating gate capacitance ratio in the critical area without requiring the entire floating gate to be narrow.
Solution Approach 2:
The invention addresses the area-capacitance ratio issue by transitioning from a uniform two-dimensional floating gate to a three-dimensional structure with varying width along its length. This dimensional variation allows optimization of the capacitance ratio in the active region while maintaining sufficient total area for electrical connections and electron trapping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides reliable and high-quality printing by eliminating the need for fuses, reducing the risk of damage and blockages, and improving signal-to-noise ratios, resulting in improved EPROM performance and smaller standard deviations in on-resistance.
Implementation Method 1
Each memory cell includes a transistor structure and two gates that are separated from each other by a thin dielectric layer. One of the gates is a floating gate and the other is a control gate or input gate.
Implementation Method 2
To program a memory cell, a programming voltage (e.g., 10 to 16 volts) is applied to the control gate and drain. The programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage.
Data Source
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AI summary
A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.