Floating Gate Erase Gate Coupling for Non-Volatile Memory Programming
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Solution Overview
Problem
As semiconductor process nodes shrink, the reduced coupling between structures in non-volatile memory cells, such as the erase gate and floating gate, leads to decreased performance and increased programming cycle time, necessitating higher control gate potentials or reduced programming speed.
Innovation Solution
The solution involves forming an erase gate over a common source region that overlies a portion of the floating gate, isolated by an inter-poly dielectric, increasing the capacitive coupling between the erase gate and the floating gate, thereby enhancing programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cell size is reduced to improve density, then the area for coupling between erase gate and floating gate is reduced, but the programming performance degrades
Solution Approach 1:
The patent extends the floating gate electrode in the vertical dimension beneath the control gate, creating an L-shaped or U-shaped structure. This vertical extension increases the coupling area between the erase gate and floating gate without increasing the planar footprint of the memory cell, thereby maintaining high density while improving programming speed
Solution Approach 2:
The floating gate electrode is positioned within the region defined by the control gate, with portions of the floating gate extending beneath the control gate structure. This nested arrangement allows the floating gate to be contained within the control gate's footprint while still providing extended coupling area, effectively using the control gate structure as a container that enables increased coupling without increasing overall cell area
2Quantity of substance
If the cell size is reduced to improve density, then the coupling area is reduced, but the control gate potential must be increased
Solution Approach 1:
By extending the floating gate vertically beneath the control gate, the patent increases the capacitive coupling area without requiring higher control gate potentials. The extended portion of the floating gate creates additional coupling pathways that enhance programming efficiency at lower voltages
Solution Approach 2:
The nested configuration of the floating gate within the control gate region allows for increased coupling area while maintaining compact cell dimensions. This arrangement enables effective programming at lower potentials by maximizing the overlap and proximity between the floating gate and control gate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the programming speed and performance of non-volatile memory cells by allowing lower control gate potentials during programming, reducing power consumption while maintaining or improving programming speed and efficiency.
Implementation Method 1
The coupling area of the floating gate and the erase gate that is available for coupling during a cell programming cycle is important to the cell performance
Data Source
AI summary
Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.