Floating-Gate Memory Cell Structure for Low-Stress Erase Paths
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Solution Overview
Problem
Conventional non-volatile memory devices face reliability issues during programming and erase operations due to damage to the tunneling oxide layer, which affects the efficiency and speed of data erasure.
Innovation Solution
A non-volatile memory device with a novel structure including a select gate, a control gate with a non-vertical surface, a floating gate with vertical and horizontal portions, and an erase gate that covers the non-vertical surface and tips of the floating gate, allowing for efficient electron discharge during erasure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrons are injected into or pulled out of the floating gate through the tunneling oxide layer during programming or erase operations, then the operating voltage and efficiency are improved, but the tunneling oxide layer structure is damaged and reliability is reduced
Solution Approach 1:
The floating gate is segmented into multiple portions (first floating gate portion, second floating gate portion, third floating gate portion) with different configurations. Each portion has tailored tip structures (first tip, second tip, third tip) that enable selective electron discharge paths, reducing stress on the tunneling oxide layer while maintaining efficient erase operations.
Solution Approach 2:
Different regions of the floating gate are given different local structures: the first floating gate portion has a first tip laterally spaced from the control gate, the second floating gate portion has a second tip vertically spaced apart, and the third floating gate portion has a third tip laterally spaced. This local differentiation allows optimized electron discharge at each location, improving overall erase efficiency while protecting the tunneling oxide layer.
2Reliability
If an erase gate is added to pull electrons from the floating gate through the tunneling oxide layer on the floating gate, then reliability is improved, but device complexity increases
Solution Approach 1:
The control gate is designed with a non-vertical surface that serves multiple functions: it controls the channel for programming operations and also works in conjunction with the segmented floating gate portions to enable efficient erase operations. The control gate's extended surface area and specific geometry allow it to participate in both programming and erasing functions, reducing the need for additional dedicated structures.
Solution Approach 2:
The floating gate portions are positioned in different spatial dimensions relative to the control gate: lateral spacing in the horizontal dimension, vertical spacing in the vertical dimension. This multi-dimensional arrangement creates multiple discharge paths without requiring additional gates, as the existing control gate structure can interact with all floating gate portions through its extended non-vertical surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances the reliability and efficiency of data erasure by reducing the stress on the tunneling oxide layer and enabling effective electron discharge through optimized tip configurations, improving the overall performance of the memory device.
Implementation Method 1
electrons have to be injected into or pulled out of the floating gate through a tunneling oxide layer disposed under the floating gate
Implementation Method 2
an erase gate is adopted and incorporated into to the memory device, which is capable of pulling the electrons from the floating gate by applying a positive voltage to the erase gate
Data Source
AI summary
A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.