Floating-Gate Memory Cell Layout for Stable Erase Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memory devices face reliability issues due to misalignment of the erase gate, leading to variations in erase voltage and non-uniform electrical characteristics, which affect the efficiency and consistency of data erasure.
Innovation Solution
The proposed non-volatile memory device incorporates an assist gate structure with a tunneling dielectric layer and an upper gate structure that covers the floating gate, allowing for reduced voltage variation and improved uniformity even with misalignment, by embedding the first top edges of the floating gate within the upper gate structure and extending beyond the second sidewalls, thereby maintaining consistent electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an erase gate is incorporated into the memory device to pull electrons from the floating gate, then the reliability of the memory device is improved, but the misalignment of the erase gate causes significant changes in the coupling ratio between the erase gate and the floating gate, increasing variation in required erase voltage and deteriorating uniformity in electrical characteristics
Solution Approach 1:
The upper gate structure extends in the second direction (width direction) beyond the floating gate, creating a three-dimensional configuration where the gate coupling occurs through both vertical and lateral dimensions. This dimensional extension ensures that even with misalignment in the vertical direction, the lateral overlap maintains consistent coupling ratio, thereby resolving the contradiction between reliability improvement and manufacturing precision.
Solution Approach 2:
The patent changes the geometric parameters of the upper gate structure by extending it beyond the floating gate sidewalls in the second direction. This parameter modification (increasing the gate width beyond the floating gate width) compensates for vertical misalignment and maintains stable coupling ratio, thus improving manufacturing precision while preserving the reliability benefits of the erase gate structure.
2Productivity
If electrons are injected into or pulled out of the floating gate through a tunneling oxide layer during programming or erase operations, then the operating voltage and speed are increased, but the structure of the tunneling oxide layer is damaged, reducing the reliability of the memory device
Solution Approach 1:
The patent divides the gate structure into multiple segments: an assist gate structure and an upper gate structure (control gate). This segmentation allows the programming operation to use the assist gate for electron injection through the tunneling oxide layer, while the upper gate structure is primarily used for erase operations that pull electrons out through a different path, thereby distributing the stress and reducing cumulative damage to the tunneling oxide layer while maintaining high operating speed.
Solution Approach 2:
The assist gate structure acts as an intermediary that facilitates electron injection during programming operations. By using the assist gate as a mediator for the programming process, the direct interaction between the control gate (upper gate structure) and the tunneling oxide layer during programming is reduced, allowing the control gate to focus on erase operations where it can more effectively pull electrons out without causing as much damage to the tunneling oxide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the uniformity of electrical characteristics and reduces voltage variation, improving the efficiency and reliability of data erasure in non-volatile memory devices, addressing the misalignment issues and enhancing overall performance.
Implementation Method 1
the upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure
Implementation Method 2
electrons are injected into or pulled out of the floating gate through a tunneling oxide layer
Data Source
AI summary
A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.