Floating-Gate Semiconductor Detector for Powerless EUV Intensity Sensing
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Solution Overview
Problem
Current semiconductor patterning processes face challenges in maintaining reliability and yield as feature sizes decrease, with existing methods for patterning material layers in semiconductor wafers being insufficient for achieving consistent results, particularly in high-density and complex circuit designs.
Innovation Solution
The development of high-density, powerless semiconductor detectors for extreme ultraviolet (EUV), deep ultraviolet (DUV), and e-beam light detection, utilizing a semiconductor detector structure with two transistors coupled in series, where a floating gate stores electrical charge proportional to light or e-beam intensity, allowing for detection and adjustment of light sources without power application during the detection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction and lithography parameter adjustments are used to mitigate defects, then patterning quality can be improved, but process complexity and time consumption increase
Solution Approach 1:
The patent applies preliminary action by performing detection and measurement of light intensity and uniformity before the actual patterning process. The semiconductor detector measures the light profile in advance, allowing for pre-correction of lithography parameters and identification of potential defects before they affect production, thereby reducing the need for complex post-processing corrections
Solution Approach 2:
The semiconductor detector enables self-service by providing real-time feedback on light intensity and uniformity directly at the patterning location. This self-measurement capability allows the system to automatically detect and compensate for variations without requiring external complex measurement systems, simplifying the overall process while maintaining high precision
2Measurement precision
If conventional detection methods with power application are used, then detection capability is achieved, but additional power consumption and potential interference with light measurement occur
Solution Approach 1:
The semiconductor detector operates in a powerless detection mode where the detector units themselves serve as the measurement elements without requiring external power application during detection. The floating gate transistors naturally respond to light intensity through charge accumulation, enabling measurement without active power consumption that could interfere with the light field being measured
Solution Approach 2:
The patent replaces conventional active electronic detection systems with a passive semiconductor detector system based on floating gate transistor charge accumulation. This substitution eliminates the need for powered sensors or active measurement components that would consume energy and potentially interfere with the light measurement, using instead a passive physical effect-based detection mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise detection and adjustment of light intensity, improving patterning quality and uniformity, thereby enhancing the reliability and yield of semiconductor manufacturing processes, especially in complex designs like FinFETs, by using a powerless detection mode that directly measures light or e-beam intensity without additional power consumption.
Implementation Method 1
a floating gate stores electrical charge proportional to light or e-beam intensity
Data Source
AI summary
A semiconductor structure includes a substrate, a semiconductor detector, a peripheral circuit, and a multilayer interconnection structure. The substrate has a sensing region and a peripheral region. The semiconductor detector is on the sensing region of the substrate. The semiconductor detector includes a first detector unit, a second detector unit, and a third detector unit. Each of the first, second, third detector units includes a first transistor and a second transistor connected in series. A gate of the second transistor is a floating gate. The peripheral circuit is on the peripheral region of the substrate and is coupled to the semiconductor detector. The multilayer interconnection structure is over the substrate. A first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector.