2D Floating-Gate Flash Synapse for Sneak Path Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In neuromorphic computing systems, two-terminal memristor-based synaptic devices face issues with sneak path leakage current, which hinders high-speed and low-power data processing, and three-terminal devices offer advantages but require additional selector devices, increasing chip area.
Innovation Solution
A flash memory device with a substrate, channel layer made of two-dimensional materials like MoS2, a tunneling insulating layer, a floating gate, and a blocking insulating layer, where the channel layer and floating gate are formed using specific materials and processes to improve tunneling efficiency and prevent sneak path leakage, reducing chip area and enhancing non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-terminal memristor-based synaptic devices are used, then device simplicity is maintained, but sneak path leakage current increases
Solution Approach 1:
The patent introduces a three-terminal flash memory device structure where the gate acts as an intermediary control element. The gate terminal mediates between the source and drain, enabling independent control of the tunneling current path. This intermediary structure effectively blocks sneak path leakage currents that plague two-terminal devices, as the gate can be used to control when current flows through the channel layer.
Solution Approach 2:
The patent transitions from a two-terminal to a three-terminal device configuration, adding a vertical dimension of control. By introducing the gate terminal as a separate control dimension, the device gains the ability to independently modulate current flow without requiring additional selector devices in series, thus solving the sneak path problem while maintaining array scalability.
2Object-generated harmful factors
If three-terminal devices with additional selector devices are used, then sneak path leakage is prevented, but chip area increases
Solution Approach 1:
The three-terminal flash memory device structure serves multiple functions simultaneously: the gate terminal provides both the control function needed to prevent sneak path leakage and the weight storage function for synaptic operations. This multi-functional design eliminates the need for separate selector devices, reducing chip area while maintaining the ability to block leakage currents effectively.
Solution Approach 2:
The patent merges the selector function and the memory/storage function into a single integrated three-terminal device structure. The gate terminal combines the roles of a selector switch and a control electrode, eliminating the need for additional external selector devices and thereby reducing the overall chip area required for synaptic device arrays.
3Reliability
If conventional synaptic devices are used, then basic memory function is achieved, but non-linearity is insufficient for efficient neuromorphic computing
Solution Approach 1:
The patent utilizes adjustable parameters including the thickness of the tunneling insulating layer and blocking insulating layer, the dielectric constants of these layers, and the materials composition to precisely control the non-linearity of the device. By changing these parameters, the device can achieve high non-linear transfer characteristics while maintaining reliable memory function, enabling efficient neuromorphic computing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed flash memory device improves synaptic weight non-linearity and reduces power consumption, enabling efficient neuromorphic computing by emulating spike-timing-dependent plasticity and supporting spiking neural networks with robust synaptic updates and learning capabilities.
Implementation Method 1
a tunneling insulating layer disposed on the channel layer and having a first dielectric constant
Implementation Method 2
a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant
Data Source
AI summary
A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.