Floating Gate GAA Structure for High-Frequency Decoupling Capacitance
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Solution Overview
Problem
Conventional approaches to integrating decoupling capacitors in semiconductor devices result in channel capacitance loss and increased complexity, particularly at high frequency operations, due to limited metal volume and metal resistance issues in the sheet-to-sheet spaces.
Innovation Solution
The proposed solution involves inserting floating gate layers between semiconductor sheets and capping them with an insulating layer and gate electrode layer, maintaining high channel inversion capacitance by optimizing metal resistance and utilizing a thicker dielectric layer to share voltage drops, thus reducing capacitance loss and enabling high voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used to integrate decoupling capacitors, then device complexity is reduced, but channel capacitance is lost and metal resistance increases at high frequencies
Solution Approach 1:
The patent merges the decoupling capacitor function with the gate structure by forming the capacitor within the gate-all-around configuration. The gate electrode serves dual purposes: as the gate control electrode and as one of the capacitor electrodes, eliminating the need for separate capacitor structures and reducing device complexity while maintaining high channel inversion capacitance at high frequencies
Solution Approach 2:
The gate structure is designed to perform multiple functions simultaneously: it acts as both the gate control element for the transistor and as part of the decoupling capacitor structure. This multi-functionality allows the same structural elements to provide both switching control and voltage decoupling, reducing overall device complexity while maintaining performance
2Area of stationary object
If metal volume is limited in sheet-to-sheet spaces, then device area is reduced, but metal resistance increases and capacitance is lost
Solution Approach 1:
The patent transitions from planar capacitor structures to a three-dimensional gate-all-around configuration where the capacitor structure extends vertically around the channel. This dimensional change allows for increased effective capacitor area and improved metal volume utilization within the same footprint, reducing metal resistance while maintaining high capacitance
Solution Approach 2:
The capacitor structure is nested within the gate-all-around configuration, where the gate electrode and capacitor electrode are integrated in a nested arrangement. This nesting allows maximum utilization of the available space between sheets, increasing effective metal volume and capacitance without increasing the device footprint
3Reliability
If capacitors are added to maintain supply voltage, then voltage stability is improved, but overhead space is consumed that could be used for valuable functions
Solution Approach 1:
The decoupling capacitor function is merged with the gate structure, eliminating the need for separate capacitor blocks that would consume overhead space. The same structural elements provide both gate control and voltage decoupling, freeing up chip area for additional functional circuits while maintaining voltage stability
Data Source
AI summary
A semiconductor device and a method of manufacturing the semiconductor device are provided. The method includes the following steps. A plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate are formed. The second semiconductor layers are removed to form openings between the first semiconductor layers. A plurality of gate dielectric layers is formed, and each of the gate dielectric layers surrounds one of the first semiconductor layers respectively. A plurality of floating gate layers is formed, wherein the floating gate layers are electrically connected to each other and surround the gate dielectric layers respectively, and the gate dielectric layers are located between the first semiconductor layers and the floating gate layers respectively.