Floating Gate Isolation Layout Using Implanted Regions
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Solution Overview
Problem
As semiconductor devices shrink, the narrow top and wide bottom design of floating gates in NOR flash memory leads to adjacent gates interfering with each other, requiring a method to reduce dielectric coefficient between them.
Innovation Solution
An ion implantation process is used to form implanted regions between patterned semiconductor structures embedded in an isolation structure, reducing dielectric coefficient and preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the floating gate is made with narrow top and wide bottom to facilitate control gate formation, then the control gate can be properly formed, but the bottoms of adjacent floating gates become too close causing interference
Solution Approach 1:
The patent introduces an implanted region as an intermediary structure between adjacent floating gates. This implanted region, formed by ion implantation into the isolation structure, acts as a mediator that electrically isolates the adjacent floating gates while allowing them to maintain their narrow-top wide-bottom geometry for proper control gate formation.
Solution Approach 2:
The patent applies local quality by creating implanted regions with specific electrical properties only in the isolation structure between adjacent floating gates. This localized modification changes the dielectric coefficient only where needed, maintaining the overall device structure while preventing interference between specific adjacent gates.
2Productivity
If the size of semiconductor devices is reduced, then device density increases, but the isolation structure width must be reduced causing adjacent floating gates to interfere
Solution Approach 1:
The patent changes the electrical parameter (dielectric coefficient) of the isolation structure by forming implanted regions through ion implantation. This parameter change allows the isolation structure to maintain electrical isolation between gates even when the physical dimensions are reduced for higher device density.
3Reliability
If ion implantation is performed to form implanted regions between floating gates, then dielectric coefficient is reduced preventing interference, but additional process steps are added
Solution Approach 1:
The patent performs ion implantation into the isolation structure before forming the floating gates. This preliminary action prepares the isolation structure with the correct electrical properties in advance, ensuring that when floating gates are later formed and positioned close together, they are already electrically isolated by the implanted regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces dielectric coefficient between patterned semiconductor structures, preventing interference and facilitating the formation of control gates in semiconductor devices.
Implementation Method 1
An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure
Data Source
AI summary
The method of forming the semiconductor device includes the following steps. An isolation structure is formed between a plurality of active areas. Semiconductor structures are formed over the active areas, and a portion of each semiconductor structure is embedded in the isolation structure. Sacrificial structures are formed on the semiconductor structures. An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure. The sacrificial structures are removed to form patterned semiconductor structures. A dielectric structure is formed on the patterned semiconductor structure. A control structure is formed on the dielectric structure.