Floating Gate CMOS Inverter Memory Cell Layout Area Reduction
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Solution Overview
Problem
Existing non-volatile memory cells for RFID applications face challenges in achieving ultra-low power consumption, compact layout area, and efficient programming/erasing operations while maintaining low voltages and currents, as they often require excessive layout area or special circuitry for high voltage transfer.
Innovation Solution
A single-poly CMOS logic memory cell with a floating gate CMOS inverter structure that eliminates the need for direct connections between pull-up and pull-down transistor drains, allowing for a reduced layout area and efficient programming/erasing through Fowler-Nordheim tunneling without dedicated tunnel capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional non-volatile memory cell structure is used, then programming and erasing operations can be performed, but the layout area becomes excessively large
Solution Approach 1:
The patent merges the pull-up transistor and pull-down transistor into a shared inverter structure where both transistors share common diffusion regions and control gates. This consolidation eliminates redundant components and reduces the overall layout area while maintaining the ability to perform programming and erasing operations through Fowler-Nordheim tunneling.
Solution Approach 2:
The inverter structure serves multiple functions: it acts as both the readout circuit and the programming/erasing control structure. The same transistors and gates used for data reading also control the Fowler-Nordheim tunneling process, eliminating the need for separate dedicated circuitry and reducing layout complexity.
2Productivity
If additional circuitry is added for high voltage transfer, then programming and erasing operations improve, but device complexity increases
Solution Approach 1:
The memory cell structure is designed to generate and utilize the necessary high voltages for Fowler-Nordheim tunneling through its own internal components. The control gates and transistor structures themselves serve as the voltage generation and transfer mechanism, eliminating the need for external high voltage pumps or additional dedicated circuitry.
Solution Approach 2:
The control gates serve dual purposes: they control the switching operation of the transistors during readout and simultaneously generate the high voltage fields necessary for Fowler-Nordheim tunneling during programming and erasing. This multi-functionality reduces overall device complexity.
3Use of energy by moving object
If power consumption is reduced to ultra-low levels, then energy efficiency improves, but operational voltage and current margins decrease
Solution Approach 1:
The memory cell uses periodic pulsed voltages for programming and erasing operations rather than continuous power consumption. During readout operations, the cell operates at ultra-low power states, and high power is only applied momentarily during programmed erase cycles, achieving ultra-low average power consumption while maintaining adequate operational margins during active operations.
Solution Approach 2:
The patent employs Fowler-Nordheim tunneling which allows charge injection and removal at controlled voltage thresholds. By carefully controlling the voltage parameters applied to the control gates, the system achieves ultra-low power consumption during standby and read operations while maintaining sufficient voltage margins for reliable programming and erasing when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables ultra-low power operation, compact layout, and efficient programming/erasing at low voltages, suitable for high-volume logic memory applications, including RFID and future mobile technologies, by minimizing layout area and eliminating the need for additional masks or process steps.
Implementation Method 1
programmed and erased by Fowler-Nordheim (F-N) tunneling mechanism
Data Source
AI summary
A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell. In this case, the NMOS inverter transistor functions as a tunneling capacitor for programming and erasing the cell, and the PMOS inverter transistor functions as a tunneling capacitor for erasing the cell.