Nonvolatile Memory Floating Gate Formation via Dual Isolation Layer
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Solution Overview
Problem
The existing methods for manufacturing nonvolatile semiconductor memory devices face challenges in forming self-aligned floating gates due to voids and seams caused by the device isolation layer, particularly as design rules tighten and trench widths decrease, leading to deteriorated device characteristics.
Innovation Solution
A method involving the formation of a pad oxide layer pattern and a mask pattern on a semiconductor substrate, followed by etching a trench and sequentially depositing first and second device isolation layers to fill it, with careful removal of mask and pad oxide layers to create a floating gate forming region, minimizing the formation of seams and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an oxide layer is used as a device isolation layer to fill trenches, then gap-filling characteristics are improved, but the oxide layer is chemically etched by etchant during manufacturing, making it difficult to form self-aligned floating gates
Solution Approach 1:
The device isolation layer is divided into two distinct layers: a lower oxide layer for gap-filling and an upper organic material layer for self-alignment. This segmentation allows each layer to perform its specific function without interfering with the other, resolving the contradiction between gap-filling and self-alignment capabilities.
Solution Approach 2:
Different materials are used at different locations within the device isolation structure. The lower portion uses oxide material optimized for gap-filling, while the upper portion uses organic material optimized for self-alignment and etching resistance. This local differentiation allows both requirements to be satisfied simultaneously.
2Productivity
If the trench width is decreased to accommodate smaller design rules, then integration density is improved, but voids occur when the device isolation layer is formed
Solution Approach 1:
The device isolation layer uses a composite structure combining oxide material and organic material. The oxide layer provides excellent gap-filling properties for narrow trenches, while the organic material layer prevents void formation and ensures proper filling. This composite approach enables successful isolation layer formation even in narrow trenches required for small design rules.
3Reliability
If the lower width of floating gate forming regions is made wider than the upper width to compensate for etching, then self-alignment is improved, but seams and voids are generated when the floating gate is formed
Solution Approach 1:
The upper organic material layer acts as an intermediary that protects the lower oxide layer during etching processes. This intermediary layer allows for proper self-alignment through controlled etching while preventing the formation of seams and voids by maintaining structural integrity during the floating gate formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the formation of seams and voids in the element isolation layer, thereby improving the characteristics of the nonvolatile semiconductor memory device by ensuring accurate alignment and structure integrity of the floating gate.
Implementation Method 1
since the oxide layer may be chemically etched by, e.g., an etchant, during the manufacturing process of the semiconductor
Data Source
AI summary
A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.