Floating Gate Transistor Isolation Overlap for Data Retention
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Solution Overview
Problem
As dimensions and tunneling oxide of non-volatile memory cell units shrink, data retention loss and charge leakage from the floating gate become significant issues, necessitating improved data retention characteristics in nonvolatile memory structures compatible with standard logic CMOS processes.
Innovation Solution
A nonvolatile memory structure is designed with a semiconductor substrate featuring oxide define regions and isolation regions, where a floating gate transistor is completely overlapped with the underlying oxide region and partially overlapped with intervening isolation regions, reducing data retention loss and current leakage by ensuring the floating gate is entirely on the isolation region, thereby enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dimensions and tunneling oxide of memory cell unit are shrunk, then memory integration density is improved, but data retention loss and charge leakage from floating gate increase
Solution Approach 1:
The patent divides the memory cell structure into distinct regions with isolation regions separating different oxide define regions. This segmentation prevents charge leakage between adjacent memory cells while maintaining small dimensions, thus improving data retention as dimensions are shrunk.
Solution Approach 2:
The patent introduces isolation regions as intermediary structures between adjacent oxide define regions. These isolation regions act as mediators that block charge leakage paths while allowing the memory cell dimensions to be reduced for higher integration density.
2Reliability
If floating gate is made smaller to reduce leakage, then charge storage capacity is reduced, but data retention is improved
Solution Approach 1:
The patent applies different properties to different parts of the structure: the floating gate is confined to specific oxide define regions with local insulation, while isolation regions provide additional insulation in between. This local quality differentiation allows the floating gate to be small for low leakage while maintaining adequate storage capacity through optimized local charge confinement.
3Reliability
If isolation regions are added between oxide define regions, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent merges the isolation region formation with the existing oxide define region fabrication process. By combining these functions into a unified structural approach where isolation regions are integrated between oxide define regions, the patent reduces overall complexity while maintaining improved data retention characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces data retention loss and current leakage, improving the overall data retention characteristics of nonvolatile memory structures while maintaining compatibility with standard CMOS processes.
Implementation Method 1
The operation of the memory unit is based on the principle of electric capacity, i.e. induced charges are stored in the floating gate to change the threshold voltage of the memory unit for determining the data status of '0' and '1.'
Implementation Method 2
a floating gate transistor is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions
Data Source
AI summary
A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.