Integrated Circuit Layout Using Floating Gates for Routing Space
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring that standard cell layout designs meet stringent specifications and reliability requirements, with existing methods lacking efficiency in routing resources and area utilization.
Innovation Solution
A method involving the identification and replacement of dummy gate isolation patterns with floating gate patterns in integrated circuit layout designs, which allows for improved routing resources and reduced area occupation, enhancing manufacturing efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dummy gate isolation patterns are retained in the layout design, then manufacturing completeness is maintained, but routing resources are reduced and area efficiency deteriorates
Solution Approach 1:
The patent extracts and removes dummy gate isolation patterns from the layout design that do not correspond to actual transistor gates. These dummy patterns are eliminated through automated detection and replacement processes, converting them into floating gate patterns or removing them entirely, thereby freeing up routing resources and improving area efficiency while maintaining manufacturing validity through EDA tool verification
Solution Approach 2:
The patent changes the state of dummy gate isolation patterns from fixed manufacturing requirements to optional elements that can be modified. By detecting dummy patterns and applying replacement criteria, the design transitions from a state where all dummy patterns must be retained to a state where only necessary dummy patterns are kept, allowing parameter optimization of routing resources and area
2Productivity
If via patterns are retained in the layout design, then manufacturing completeness is maintained, but area efficiency deteriorates
Solution Approach 1:
The patent extracts and removes redundant via patterns from the layout design. Automated detection algorithms identify via patterns that do not correspond to necessary interlayer connections, and these are removed or optimized, thereby improving area efficiency while maintaining manufacturing validity through EDA tool verification
Solution Approach 2:
The patent changes the presence parameter of via patterns from a fixed requirement to an optimized selection. By detecting which via patterns are necessary for manufacturing and which are redundant, the design allows dynamic adjustment of via pattern inclusion, optimizing area efficiency while preserving manufacturing completeness
Data Source
AI summary
An integrated circuit includes a first and second active region extending in a first direction, and a floating gate, a first dummy gate, a first conductor and a second conductor extending in the second direction. The floating gate is electrically floating. The first dummy gate is separated from the floating gate in the second direction. The dummy gate and the floating gate separate a first cell that corresponds to a first transistor from a second cell that corresponds to a second transistor. The first and second conductors are separated from each other in the first direction, and overlap the second active region. The first and second conductors are electrically coupled to a corresponding source/drain of the second active region, and are configured to supply a same signal/voltage to the corresponding source/drain of the second active region. The floating gate is between the first and second conductors.