Floating-Gate Memory Cell Structure for Low-Voltage Program and Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices face challenges in achieving low area penalty and low power consumption while efficiently programming and erasing data.
Innovation Solution
The proposed non-volatile memory device incorporates a memory cell structure with a select transistor, a floating gate transistor, and a metal conductor, which allows for programming by channel hot electron injection and erasing by band-to-band hot hole injection, eliminating the need for additional area to drive out electrons from the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional EEPROM programming/erasing methods are used, then data can be stored and erased, but additional area is required to drive out electrons from the floating gate
Solution Approach 1:
The patent extracts the electron removal function from the conventional floating gate structure by introducing a separate erasure gate. This allows electrons to be removed through band-to-band hot hole injection at the erasure gate interface, eliminating the need for additional area that would otherwise be required for conventional erasure mechanisms.
Solution Approach 2:
The patent introduces a tunnel oxide layer as an intermediary between the floating gate and the erasure gate. This tunnel oxide enables controlled electron transport through tunneling and hot hole injection mechanisms, facilitating efficient erasure without requiring additional area while maintaining manufacturability.
2Productivity
If higher operation voltages are used for programming and erasing, then carrier injection efficiency improves, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter distribution by using separate control gates (select gate for programming, erasure gate for erasing) that can be independently biased. This allows optimization of voltage levels for each operation, achieving high carrier injection efficiency through controlled electric fields while reducing overall power consumption by avoiding sustained high voltages.
Solution Approach 2:
The patent employs periodic switching between programming and erasing operations through the select transistor, which controls electron injection during programming and electron removal during erasing. This periodic action allows the device to operate at lower average power levels while maintaining high efficiency during active programming/erasing intervals through optimized voltage pulses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a memory cell with reduced footprint and lower power consumption, as it enables smaller operation voltages and efficient carrier injection mechanisms, thereby improving overall performance and efficiency.
Implementation Method 1
programming by channel hot electron injection
Implementation Method 2
erasing by band-to-band hot hole injection
Data Source
AI summary
A non-volatile memory device including a substrate and a memory cell. The memory cell includes a select transistor, a floating gate transistor, and a metal conductor. The select transistor includes a select gate structure over the substrate, a first source/drain region on a first side of the select gate structure, and a second source/drain region on a second side of the select gate structure opposite the first side. The floating gate transistor includes a floating gate structure over the substrate, the second source/drain region on a third side of the floating gate structure, and a third source/drain region on a fourth side of the floating gate structure opposite the third side. The metal conductor is over and electrically isolated from the floating gate structure. The floating gate transistor further includes a first low-voltage lightly doped drain between the floating gate structure and the third source/drain region.