Floating Gate Memory Cell Structure Simplification
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Solution Overview
Problem
Conventional EEPROMs have complex structures due to the need for control gate wiring and high voltage application, leading to increased manufacturing costs and incompatibility with logic processes, especially in small-capacity data storage applications.
Innovation Solution
A nonvolatile semiconductor memory device with a simplified structure that uses impurity diffusion layers to inject and eject electrons from a floating gate without a control gate, allowing for capacitive coupling and reduced voltage application, thereby simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a control gate is stacked on the floating gate to transfer electric charge, then the EEPROM can store and erase data, but the structure becomes complex and manufacturing costs increase
Solution Approach 1:
The patent removes the control gate from the conventional EEPROM structure, retaining only the floating gate. The control gate's function of transferring charge to the floating gate is replaced by directly applying high voltage to the drain to enable charge injection through tunneling, thereby simplifying the cell structure while maintaining data storage capability.
Solution Approach 2:
The drain in this invention serves multiple functions: it acts as both the source/drain for current flow during read operations and as the charge injection electrode during write operations by applying high voltage. This eliminates the need for a separate control gate, as the drain universally handles both data readout and charge transfer functions.
2Reliability
If a control gate is provided for each memory cell, then charge transfer is enabled, but wiring complexity and manufacturing difficulty increase
Solution Approach 1:
The control gate wiring is completely removed from the structure. Instead of requiring individual control gate connections for each memory cell, the invention uses the existing drain wiring to apply high voltage for charge injection, significantly reducing wiring complexity and improving compatibility with standard logic fabrication processes.
Solution Approach 2:
The control gate function is merged with the drain function. The drain not only provides the current path for read operations but also serves as the charge injection electrode during write operations by applying high voltage, thereby eliminating the need for separate control gate wiring and simplifying the overall structure.
3Reliability
If high voltage is applied to the source or drain to inject charge into the floating gate, then data writing is enabled, but the applied voltage requirements increase
Solution Approach 1:
The patent changes the voltage application parameters by applying high voltage specifically to the drain during write operations rather than to a control gate. This allows charge injection through the drain-floating gate interface while maintaining lower voltage requirements for the source and other terminals during normal operation, optimizing the energy profile of the device.
4Reliability
If EEPROM fabrication is performed independently of logic process, then EEPROM functionality is achieved, but manufacturing costs increase
Solution Approach 1:
The simplified EEPROM structure using standard n-channel MOS transistors with floating gate can be fabricated using the same CMOS process as logic circuits. The drain-based charge injection mechanism is compatible with standard fabrication processes, allowing EEPROM and logic circuits to be manufactured together on the same wafer, thereby reducing manufacturing costs while maintaining full EEPROM functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the structure of nonvolatile semiconductor memory devices, reduces manufacturing costs, and enhances compatibility with logic processes, enabling efficient write and erase operations with lower voltage requirements.
Implementation Method 1
the second impurity diffusion layer and the floating gate may be coupled together and electrons ejected from the first impurity diffusion layer may be injected into the floating gate
Data Source
AI summary
A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.