Floating Gate to Charge Trapping Memory Conversion
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Solution Overview
Problem
The existing processes for forming floating gate and charge trapping memory arrays require separate optimization due to differences in transistor structure, doping concentrations, and charge storing materials, leading to the need for distinct masks and layout designs, which complicates the manufacturing and conversion between these two types of non-volatile memory technologies.
Innovation Solution
A method and system are developed to convert a design for a floating gate memory array to a charge trapping memory array, and vice versa, by modifying the transistor type, charge pump configuration, and I/O interface, using a processor to adjust the layout and manufacturing instructions, allowing for the use of fewer sets of masks and reducing production complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used for forming floating gate memory and charge trapping memory, then each memory type can be optimized for its specific requirements, but the device complexity and manufacturing cost increase due to needing separate masks and layout designs
Solution Approach 1:
The patent applies universality by creating a single layout design that can be used for both floating gate memory and charge trapping memory formation. The method enables one mask set to serve multiple memory types by adjusting process parameters rather than requiring separate dedicated masks for each memory technology, thereby reducing manufacturing complexity while maintaining optimization capabilities.
Solution Approach 2:
The patent utilizes parameter changes by modifying process conditions such as doping concentrations, well depths, and charge pump configurations to adapt the same layout design for different memory types. This allows the manufacturing process to be tuned for specific memory requirements without changing the fundamental layout or mask set, resolving the contradiction between optimization and complexity.
2Manufacturing precision
If separate masks and layout designs are used for each memory type, then manufacturing precision for each specific memory can be maximized, but the ease of manufacture decreases due to additional manufacturing steps
Solution Approach 1:
The invention enables a single layout design to serve dual purposes for both floating gate and charge trapping memory formation. This universal approach maintains manufacturing precision by allowing process parameter adjustments while eliminating the need for separate mask sets and layout designs, thereby improving ease of manufacture.
Solution Approach 2:
The patent merges the manufacturing processes for different memory types by using common masks and layout designs. The method combines previously separate fabrication workflows into a unified process that can produce different memory types from the same starting layout, reducing the number of manufacturing steps while preserving the ability to achieve precise memory cell formation.
3Reliability
If different transistor structures and doping concentrations are used for each memory type, then the reliability of each memory type is improved, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting doping concentrations, well depths, and transistor dimensions within a unified layout framework. This allows the process to achieve the specific reliability requirements for different memory types through parameter optimization rather than structural differentiation, thereby maintaining reliability while reducing device complexity.
Solution Approach 2:
The invention creates a universal transistor structure design that can be adapted for different memory types through parameter adjustments. The same basic transistor layout and mask set can produce reliable floating gate or charge trapping memory by modifying doping profiles and dimensional parameters, eliminating the need for fundamentally different transistor structures for each memory type.
Data Source
AI summary
A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.