Floating Gate Memory Coupling Ratio via 3D Stacking
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Solution Overview
Problem
Current floating gate type flash memory devices have limitations that may prevent the transition to charge trap flash memory devices, despite predictions of their future adoption, due to inferior reliability compared to charge trap type devices.
Innovation Solution
The development of nonvolatile memory devices with an increased coupling ratio between the charge storage element and electrodes, featuring a floating gate and wordlines with specific insulation layers and geometries, and a method of manufacturing and operating these devices to enhance capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate type flash memory devices are used, then superior reliability is achieved, but the coupling ratio between charge storage element and electrodes is limited
Solution Approach 1:
The patent transitions from planar 2D memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction with wordlines and bitlines extending through multiple levels, enabling increased coupling ratio while maintaining reliability through the 3D architecture
Solution Approach 2:
The patent implements nested structures where conductive plugs are formed within vias that extend through insulating layers, and memory cells are stacked within a three-dimensional structure. The wordlines and bitlines are nested through multiple levels, creating a compact high-density structure with improved coupling
2Adaptability or versatility
If charge trap flash memory devices are used, then future adoption is predicted, but inferior reliability compared to floating gate type devices
Solution Approach 1:
The patent applies different material properties to different regions: the charge storage layer uses specific dielectric materials with tailored properties, the tunnel insulation layer uses silicon oxide, and the blocking insulation layer uses materials with different breakdown characteristics. This local differentiation optimizes both reliability and charge trap functionality
3Device complexity
If insulation layers are made thinner to increase coupling ratio, then capacitive coupling improves, but insulation effectiveness may be compromised
Solution Approach 1:
The patent uses composite insulation structures with multiple layers having different dielectric properties. The tunnel insulation layer and blocking insulation layer are formed as separate composite structures, allowing thin overall thickness for high coupling while maintaining insulation effectiveness through the combined properties of different materials
Solution Approach 2:
The patent changes the dielectric constant parameters of the insulation layers by selecting materials with different permittivity values. The tunnel insulation layer and blocking insulation layer have different dielectric properties, enabling thin thickness while maintaining electrical isolation and improving capacitive coupling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the capacitive coupling between the floating gate and wordlines, potentially maintaining the dominance of floating gate type flash memory devices by enhancing their performance and reliability.
Implementation Method 1
Embodiments of the inventive concept provide nonvolatile memory devices having an increased coupling ratio between a charge storage element and corresponding electrodes
Data Source
AI summary
A floating gate type nonvolatile memory device comprises a semiconductor layer, wordlines crossing over the semiconductor layer, and a memory element disposed between the wordlines and facing the semiconductor layer.