Floating Gate Memory for Electronic Shelf Labels
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Solution Overview
Problem
Conventional display devices with memory-in-pixel (MIP) technology face challenges in reducing power consumption and increasing resolution due to the use of DRAM for refresh operations and SRAM's large-scale circuitry, which also increases the risk of wiring short circuits and lowers yield rates.
Innovation Solution
A display device comprising sub-pixels with a memory block that includes a first transistor with a floating gate for storing sub-pixel data and a second transistor with a floating gate electrically coupled to the first transistor, where one source/drain is coupled to a power supply potential, allowing for efficient data storage and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If DRAM is used as memory in each pixel, then power consumption increases due to refresh operations
Solution Approach 1:
The patent extracts the memory function from conventional DRAM/SRAM and implements it using a floating gate transistor structure. The floating gate stores charge to represent binary data, eliminating the need for continuous refresh operations while maintaining data retention capability. This extraction of the memory function to a different physical mechanism (floating gate charge storage) resolves the contradiction between power consumption and data retention.
Solution Approach 2:
The patent changes the fundamental parameter of memory storage from volatile (DRAM/SRAM) to non-volatile by using floating gate charge storage. The floating gate transistor structure allows data to be stored as electric charge in the floating gate, which retains data even without power supply. This parameter change from volatile to non-volatile storage eliminates refresh operations and reduces power consumption while maintaining reliability.
2Manufacturing precision
If SRAM is used as memory in each pixel, then circuit scale increases and resolution cannot be increased
Solution Approach 1:
The patent extracts the memory function from large-scale SRAM circuits and implements it using a compact floating gate transistor structure. Each pixel requires only a minimal number of transistors to achieve the memory function, dramatically reducing the circuit scale compared to conventional SRAM. This extraction enables higher resolution by fitting more pixels in the same area.
3Reliability
If SRAM is used with high wiring density, then wiring short circuits occur and yield rate decreases
Solution Approach 1:
The patent extracts the memory function from high-density SRAM wiring to a floating gate transistor structure that requires minimal wiring. The floating gate structure inherently provides isolation between adjacent pixels, reducing wiring density and the risk of short circuits caused by foreign matter. This extraction improves yield rate by eliminating the wiring density problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption, decreases the risk of wiring short circuits, and increases resolution by minimizing transistor and wiring density, while maintaining sub-pixel data even after the power supply is stopped.
Implementation Method 1
a first transistor (WT) including a first floating gate (WTg) and configured to store the sub-pixel data based on an electric charge in the first floating gate (WTg)
Implementation Method 2
a second transistor (RT) including a second floating gate (RTg) electrically coupled to the first floating gate (WTg) of the first transistor, one of a drain and a source of the second transistor being coupled to a power supply potential, the other of the drain and the source being coupled to a node
Data Source
AI summary
According to an aspect, a display device includes a plurality of sub-pixels arranged in a row direction and a column direction, and each including a memory block that has at least one memory configured to store sub-pixel data. The at least one memory includes: a first transistor including a first floating gate and configured to store the sub-pixel data based on an electric charge in the first floating gate; and a second transistor including a second floating gate electrically coupled to the first floating gate of the first transistor, one of a drain and a source of the second transistor being coupled to a power supply potential, the other of the drain and the source being coupled to a node. Each of the sub-pixels is configured to display an image based on a potential of the node.