Floating Gate Memory Cell With Halo Region And Thick Oxide
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Solution Overview
Problem
Existing memory technologies face challenges in reducing latency and power consumption, particularly in applications like RFID tags where low voltage operation and efficient data storage are crucial, and existing bit cell designs either lack reliability or increase device size to prevent leakage.
Innovation Solution
A solid-state non-volatile memory device using a field effect transistor (FET) with a floating gate and thick oxide layer, combined with a halo region and native doping, which allows for efficient data storage with reduced power consumption and improved reliability by using redundant floating gates and a reference current circuit for accurate data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a differential bit cell design is used to improve reliability, then reliability is improved, but device size increases and power consumption increases
Solution Approach 1:
The invention segments the bit cell into two independent storage elements, each capable of storing data independently. This segmentation allows the cell to achieve differential reliability benefits while using fewer shared components (like a single read device), thereby reducing overall device size compared to traditional differential designs.
Solution Approach 2:
The read device serves multiple functions: it can read from either of the two storage elements and is shared between both storage paths. This multi-functionality reduces the total number of read devices needed, decreasing device size while maintaining the reliability benefits of differential design.
2Reliability
If a differential bit cell design is used to improve reliability, then reliability is improved, but power consumption increases
Solution Approach 1:
The read device is designed to be shared between two storage elements, performing multiple read operations with a single device. This reduces the total number of active components consuming power during read operations, thereby lowering dynamic power consumption while maintaining differential reliability.
Solution Approach 2:
The invention merges the read functionality for two storage elements into a single shared read device. By combining these functions, the total power consumption is reduced compared to having separate read devices for each storage element, while still providing the reliability benefits of differential design.
3Duration of action of stationary object
If a thick oxide layer is used in the floating gate to improve data retention, then data retention is improved, but manufacturing complexity increases
Solution Approach 1:
The invention changes the oxide layer thickness parameter to a specific optimal value that provides sufficient data retention while remaining compatible with standard manufacturing processes. This parameter optimization ensures long data retention without requiring excessively complex manufacturing steps.
Solution Approach 2:
The thick oxide layer is applied specifically to the floating gate region where charge storage is needed, rather than uniformly across the entire device. This localized approach provides the necessary data retention in critical areas while keeping the overall manufacturing process simpler and more efficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient data storage with reduced power consumption and improved reliability, allowing for accurate data reading even if one memory element leaks, while maintaining a compact device size suitable for low-power applications like RFID tags.
Implementation Method 1
The floating gate includes a thick gate oxide layer
Implementation Method 2
The drain is fabricated within the substrate to have a halo region
Data Source
AI summary
A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.