Floating Gate Memory Reference Current Generation

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Solution Overview

Problem

Existing non-volatile semiconductor memory devices with charge accumulation on floating gates face issues of increased read circuitry scale, complex operation sequences, and poor adjustability of reference currents due to the need for multiple reference cells and complicated circuit configurations.

Innovation Solution

A non-volatile semiconductor memory device design that uses a single 'erased' reference cell with independently controlled voltage levels to generate a reference current, reducing the need for intermediate current generation circuits and simplifying the operation sequence by eliminating the need for programming the reference cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple reference cells (programmed and erased states) are connected to each wordline to generate reference current, then the reference current generation capability is improved, but the read circuitry scale increases

Engineering Contradiction:

Improvereference current generation capabilityVSAvoidread circuitry scale

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts only the erased-state reference cell from the conventional dual-reference-cell configuration. By removing the programmed reference cell and retaining only the erased reference cell, the circuit scale is reduced while still achieving reliable reference current generation for data read operations.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The erased reference cell is designed to serve multiple functions: it generates the reference current for comparison and provides a universal reference level that works for all read operations. This multi-functional design eliminates the need for separate programmed and erased reference cells.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If converting circuits and adder circuits are added to generate intermediate level current from multiple reference cells, then the reference current adjustability is improved, but the read circuitry scale and complexity increase

Engineering Contradiction:

Improvereference current adjustabilityVSAvoidread circuitry scale

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The invention removes the converting circuits and adder circuits from the system. By extracting these complex components, the design achieves reference current generation without the need for intermediate current calculation circuits, significantly reducing read circuitry scale.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The erased reference cell inherently provides the reference current with appropriate current levels through its own characteristics, without requiring external converting or adding circuits. The reference cell serves itself to generate the necessary reference current for comparison operations.

Inventive Principle:

Principle #25Self-service

3Measurement precision

If both programmed and erased reference cells are used in the read operation, then the data identification accuracy is improved, but the operation sequence becomes complicated

Engineering Contradiction:

Improvedata identification accuracyVSAvoidoperation sequence complexity

Core Design Contradiction:

Measurement precisionVSEase of operation

Solution Approach 1:

The invention removes the programmed reference cell from the read operation configuration. By eliminating this component, the complicated programming operation sequence for the programmed reference cell is removed, simplifying the overall operation sequence while maintaining data identification accuracy through the erased reference cell alone.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using both programmed and erased reference cells as in conventional designs, the invention inverts the approach by using only the erased reference cell. This inverted configuration simplifies the operation sequence while still achieving accurate data identification through the reference current provided by the erased reference cell.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS7599221B2Floating gate memory device with improved reference current generation

Publication Date: 2009.10.06 RENESAS ELECTRONICS CORP

AI summary

A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline.