Floating Gate Memory Segmentation for Charge Retention
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Solution Overview
Problem
Non-volatile memory points face significant charge leakage issues due to thin insulating layers, which worsen with repeated programming and erasing operations, leading to reduced retention capacity.
Innovation Solution
The implementation of a non-volatile memory point design featuring a floating gate with active and inactive portions, where active portions are insulated by thin layers and inactive portions by thick layers that do not conduct electrons, utilizing PN junctions to trap charges and prevent leakage, along with coupling electrodes for electron transfer and voltage modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If thin insulating layers are used to insulate the floating gate from the substrate, then the memory point can be programmed and erased more efficiently, but charge leakage increases significantly due to tunnel effect
Solution Approach 1:
The floating gate is divided into active portions (insulated by thin insulating layers for efficient programming/erasing) and inactive portions (insulated by thick insulating layers for charge retention). This segmentation allows different regions to serve different functions, resolving the contradiction between programming efficiency and charge retention.
Solution Approach 2:
Different insulating layer thicknesses are applied to different portions of the floating gate based on their functional requirements. Active portions use thin insulating layers for efficient charge injection, while inactive portions use thick insulating layers to prevent charge leakage, creating local quality variations that optimize overall performance.
2Adaptability or versatility
If multiple programming and erasing operations are performed, then the memory point can be rewritten, but the quality of the thin insulating layer deteriorates and tunnel-effect leakages increase
Solution Approach 1:
The floating gate is segmented into active and inactive portions with different insulating layer thicknesses. The inactive portions with thick insulating layers serve as stable charge storage regions that are not affected by repeated programming/erasing operations, maintaining reliability while allowing reprogrammability through the active portions.
Solution Approach 2:
Thick insulating layers are pre-applied to inactive portions of the floating gate before any programming operations occur. This beforehand cushioning protects these regions from degradation during subsequent programming and erasing cycles, ensuring long-term charge retention capacity.
3Productivity
If the floating gate is completely active with thin insulating layers, then programming and erasing operations are efficient, but charge leakage occurs during retention periods
Solution Approach 1:
The floating gate is segmented into active portions for efficient programming/erasing and inactive portions for charge retention. The inactive portions with thick insulating layers act as charge traps that prevent leakage, while active portions maintain operational efficiency.
Solution Approach 2:
The tunnel effect, which causes harmful charge leakage in conventional designs, is converted into a beneficial mechanism by using it to inject charges into the inactive portions during programming, where the thick insulating layers then prevent unwanted leakage, transforming the potential harm into a useful charge storage mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces electron leakage during retention periods, maintaining high charge retention capacity even after multiple operations, and minimizes the influence on transistor threshold voltage.
Implementation Method 1
inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons
Implementation Method 2
the inactive portions comprising at least one N-type doped area forming a portion of a PN junction
Implementation Method 3
the charges stored in floating gate 5 tend to pass, by tunnel effect, through insulating layer 8 towards the semiconductor regions of transistors T1 and T2
Data Source
AI summary
A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.


