Floating Gate Memory With Segmented Channel Regions
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Solution Overview
Problem
Existing floating gate non-volatile memory (FG NVM) technologies face challenges in achieving efficient programming current responsiveness and high-density memory cell fabrication, particularly with source-side injection methods that require additional lithographic sequences and result in larger memory cells.
Innovation Solution
The development of a multi-gated active structure with discontinuous charge storage elements and a unique channel structure that utilizes ion implantation and thermal cycles to form conductive gates and charge storage layers, allowing for improved channel structures and programming efficiency, and separate channel regions for read and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If source-side injection is used for programming, then programming current efficiency is improved, but memory cell size increases due to additional lithographic sequences
Solution Approach 1:
The channel region is segmented into multiple distinct regions (first channel region, second channel region, third channel region) with different doping concentrations and functions. This segmentation allows source-side injection programming without requiring additional lithographic sequences, as the doping profiles are formed through selective ion implantation in sequential steps, thereby maintaining small memory cell size while achieving efficient programming current responsiveness.
Solution Approach 2:
The first channel region with higher doping concentration is formed preliminarily before the second and third channel regions. This preliminary doping creates a foundation that enables subsequent programming operations to be performed without additional lithographic steps, as the dopant profiles are established through thermal diffusion and ion implantation sequences that prepare the structure in advance for efficient source-side injection programming.
2Power
If conventional hot carrier injection is used, then programming current is high, but programming efficiency is low
Solution Approach 1:
Different channel regions are assigned different doping concentrations and functions to optimize local properties. The first channel region has higher doping for robust conduction, while the second and third regions have lower doping to facilitate hot carrier generation and injection. This local quality differentiation enables the structure to respond efficiently to programming current while maintaining appropriate current levels, resolving the contradiction between high programming current and low efficiency.
3Use of energy by moving object
If memory cells are designed for source-side injection, then programming efficiency improves, but fabrication complexity increases
Solution Approach 1:
The multi-gated active structure with discontinuous charge storage elements serves multiple functions: it enables source-side injection programming, provides separate channel regions for read and programming operations, and allows for high-density fabrication. The same structural elements (channel regions, gates, charge storage regions) perform multiple roles, eliminating the need for additional specialized components that would increase fabrication complexity.
Solution Approach 2:
The invention transitions from planar channel structures to vertically stacked multi-gated structures with channel regions at different heights and positions. This dimensional change allows multiple functional regions to coexist within a compact footprint, enabling source-side injection programming without increasing lateral memory cell dimensions or requiring additional lithographic sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming current responsiveness and read current efficiency while reducing memory cell size, facilitating the fabrication of high-density floating gate memories in commercial volumes.
Implementation Method 1
The development of a multi-gated active structure with discontinuous charge storage elements and a unique channel structure that utilizes ion implantation and thermal cycles to form conductive gates and charge storage layers
Implementation Method 2
The development of a multi-gated active structure with discontinuous charge storage elements and a unique channel structure that utilizes ion implantation and thermal cycles to form conductive gates and charge storage layers
Implementation Method 3
an electrical field is generated along a channel region of a memory cell. Within the channel region, the electrical field is the highest near the drain region. The electrical field accelerates carriers flowing within the channel region, such that, within the channel region, the carriers are traveling the fastest near the drain region
Implementation Method 4
A fraction of carriers having energies large enough to overcome the dielectric barrier are hot carriers. A small fraction of these hot carriers scatter within the channel region, and they are attracted by an electrical field generated by the control gate electrode, which can help inject some into the floating gate through a dielectric region separating the channel from the floating gate
Data Source
AI summary
A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.