Floating Gate Non-Volatile Memory With Variable Capacitive Coupling
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Solution Overview
Problem
Existing non-volatile memory technologies face limitations in customization, energy efficiency, and multi-level functionality, particularly in one-time programmable (OTP) and multi-time programmable (MTP) memory devices, which often require additional processing steps and are not easily extendable to multi-bit storage.
Innovation Solution
A non-volatile memory device with a floating gate that utilizes variable capacitive coupling through multiple source/drain junctions, allowing for multiple bits of data storage and flexible programming, erasing, and integration with CMOS logic processes, enabling efficient multi-level programming and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional single-poly nonvolatile memory cells are used, then the device structure is simple, but the floating gate has minimal electrical coupling to existing electrical signals requiring additional interconnect layers
Solution Approach 1:
The patent merges the floating gate coupling function with existing source/drain junctions of the transistor. The floating gate is positioned to overlap with the source or drain region, creating direct electrical coupling through the junction without requiring separate interconnect layers. This integration eliminates additional manufacturing complexity while maintaining strong electrical coupling for programming operations.
2Ease of operation
If PMOS device structure is used for OTP, then the device can be programmed from non-conducting to conducting state, but an additional masking step is required to ensure PMOS device is in non-conducting state
Solution Approach 1:
The patent inverts the conventional OTP programming approach by using NMOS instead of PMOS. The NMOS device is programmed from a conducting state to a non-conducting state, which is the opposite of traditional PMOS OTP devices. This inversion eliminates the need for additional masking steps because the NMOS device naturally starts in a conducting state that can be reliably programmed to non-conducting through hot electron injection, simplifying the manufacturing process.
3Ease of operation
If PMOS with channel hot electron programming is used, then programming can be achieved, but the amount of energy consumption is not self-limited
Solution Approach 1:
The patent implements self-limiting energy consumption through the NMOS device structure and hot electron programming mechanism. The programming process automatically limits its own energy consumption because the hot electron injection stops when the floating gate potential reaches a threshold that prevents further electron injection. This self-regulating mechanism eliminates the need for external energy limiting circuits or complex control mechanisms, making the programming process inherently energy-efficient.
4Adaptability or versatility
If traditional OTP/MTP memories are used, then customization is provided, but additional processing steps are required
Solution Approach 1:
The patent creates a universal memory cell structure that can function as either OTP or MTP depending on the programming methodology used. The same basic NMOS device structure with floating gate overlapping source/drain junctions can be programmed once or multiple times by controlling the programming voltage and conditions. This multi-functionality eliminates the need for separate OTP and MTP device structures or additional processing steps, allowing customization while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient multi-bit storage, reduced energy consumption, and integration with existing CMOS processes, addressing the limitations of prior art by allowing for customizable and efficient programming of non-volatile memory devices.
Implementation Method 1
a programming voltage for the device applied to the drain can be imparted to the floating gate through capacitive coupling
Implementation Method 2
the device is adapted so that more than one bit of information can be stored by the programming voltage
Data Source
AI summary
A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.