Floating Gate MOSFET Unit Cell for Symmetric Neural Network Weights
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Solution Overview
Problem
Existing neural network weight implementation schemes, such as RRAM, PCM, and MRAM, are asymmetrical, which hinders their effectiveness during training.
Innovation Solution
Employing floating gate devices with a digital-to-analog converter and a resistor ladder to convert digital weights into analog values, providing a symmetrical weight scheme that is easily integratable with standard CMOS fabrication technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM, PCM, or MRAM are used for weight implementation in neural networks, then memory capacity and speed are improved, but asymmetry in weighting scheme occurs which hinders training effectiveness
Solution Approach 1:
The patent introduces floating gate MOSFETs as intermediary devices between the digital weight storage and the analog computation circuitry. These floating gate devices can be precisely controlled to provide symmetrical weight values, mediating between the digital control signals and the analog multiply-accumulate operations in the neural network processor.
Solution Approach 2:
The patent changes the physical parameter representation of weights by using floating gate charge levels to encode weight values. By controlling the amount of charge trapped in the floating gate, the invention achieves precise, symmetrical weight values that can be reliably read during computation, eliminating the asymmetry problem of previous implementations.
2Power
If cross bar arrangement with variable resistance weighting is used, then analog matrix multiplication efficiency is improved, but asymmetry in weight implementation prevents effective training
Solution Approach 1:
The patent applies local quality by giving different functional roles to different parts of the circuit. The floating gate MOSFETs are positioned at specific locations in the crossbar array to provide locally controlled, symmetrical weight values, while the overall crossbar structure maintains its analog computation capability. This localized intervention resolves the asymmetry problem without sacrificing the global efficiency of analog matrix multiplication.
3Reliability
If digital-to-analog conversion with resistor ladder is employed, then symmetrical weight scheme is achieved, but device complexity increases
Solution Approach 1:
The patent achieves multi-functionality by designing the floating gate MOSFET to perform multiple roles: it serves as a digital memory element for weight storage, as a digital-to-analog converter through its threshold voltage control, and as a switch for selecting weight values during computation. This universal device eliminates the need for separate components, reducing overall circuit complexity while maintaining symmetrical weight implementation.
Data Source
AI summary
A neural network unit cell circuit includes multiple floating gate transistors, each of the floating gate transistors having a first source/drain adapted for connection to a common bit line coupled with the unit cell circuit and having a gate adapted for connection to a corresponding one of a plurality of word lines coupled with the unit cell circuit. The unit cell further includes a resistor network having a plurality of resistors connected in a series ladder arrangement, with each node between adjacent resistors operatively connected to a second source/drain of a corresponding one of the floating gate transistors. The resistor network has a first terminal connected to a first voltage source. A readout transistor in the unit cell has a gate coupled with a second terminal of the resistor network, and has first and second source/drains generating an output voltage of the unit cell.