2D Floating-Gate MOSFET Structure for Uniform Photolithography
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Solution Overview
Problem
The height difference between transistors in the memory region and peripheral logic region of integrated circuit MOSFET devices, due to the presence of a floating gate and tunnel dielectric layer, causes focal distance variations in photolithographic processes, leading to under or over etching and residue issues.
Innovation Solution
Forming the floating gates and tunnel dielectric layers within the substrate to equalize the height of transistors in both regions, ensuring uniform focus and reducing photolithographic damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate and tunnel dielectric layers are added to memory region transistors, then memory storage capability is improved, but transistor height increases causing focal distance variations
Solution Approach 1:
The patent divides the transistor structure into distinct segments: memory region transistors with floating gate and tunnel dielectric layers for storage functionality, and peripheral logic region transistors without these layers. This segmentation allows each region to be optimized independently - memory transistors gain storage capability while peripheral transistors maintain standard height for uniform photolithographic focusing.
Solution Approach 2:
The patent applies local quality by providing different structural characteristics to different regions of the device. Memory region transistors locally incorporate floating gate and tunnel dielectric layers to achieve storage functionality, while peripheral logic region transistors maintain standard structure. This localized differentiation resolves the contradiction by allowing memory transistors to have enhanced functionality without forcing all transistors to have increased height.
2Adaptability or versatility
If transistors in memory region are made taller with floating gate structure, then flash memory functionality is achieved, but photolithographic etching precision deteriorates
Solution Approach 1:
The patent segments the device into memory region and peripheral logic region, allowing memory transistors to have the taller floating gate structure needed for flash functionality while peripheral transistors maintain standard height. This segmentation enables photolithographic processes to focus uniformly on peripheral regions without being affected by the height variations introduced by memory region structures.
Solution Approach 2:
The patent resolves the height conflict by transitioning to a planar dimension solution - placing memory and logic transistors side-by-side in the same plane rather than stacking them vertically. This dimensional arrangement allows both flash memory functionality and uniform photolithographic focusing to coexist without interference.
3Reliability
If additional layers are added to memory transistors, then storage capability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements local quality by confining the complex floating gate and tunnel dielectric layer structure exclusively to memory region transistors where storage capability is needed. Peripheral logic region transistors maintain simple standard structure without these additional layers. This localized approach enhances storage capability in necessary regions while avoiding unnecessary complexity in regions where simple logic functionality suffices.
Data Source
AI summary
A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.