Floating Gate Transistor with Segmented Intermediate Nanowire
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Solution Overview
Problem
As semiconductor devices are scaled to smaller feature sizes, maintaining a high coupling ratio between floating and control gates becomes challenging due to decreased surface area and increased inter-transistor capacitance, affecting the reliability and performance of semiconductor devices.
Innovation Solution
The design incorporates a floating gate with two end portions and an intermediate portion of reduced cross-sectional area, and a control gate with complementary shape and recesses, along with a nanowire intermediate portion, to enhance capacitance between the floating and control gates while minimizing inter-transistor capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled to smaller feature sizes, then device density and integration are improved, but the coupling ratio between floating and control gates deteriorates due to decreased surface area and increased inter-transistor capacitance
Solution Approach 1:
The floating gate is segmented into multiple portions (first floating gate portion, second floating gate portion, third floating gate portion) with varying cross-sectional areas. This segmentation allows optimization of capacitance coupling in different regions, maintaining high coupling ratio even as overall device size is reduced for higher density.
Solution Approach 2:
Different portions of the floating gate are assigned different cross-sectional areas to optimize local capacitance characteristics. The intermediate portion has reduced cross-sectional area to minimize inter-transistor capacitance, while end portions maintain larger areas for sufficient coupling with the control gate, achieving local optimization of the coupling ratio.
2Length of moving object
If the surface area between floating and control gates is decreased to enable smaller feature sizes, then device scaling is improved, but the capacitance between gates deteriorates
Solution Approach 1:
The patent extends the gate structure into the vertical dimension by creating a three-dimensional configuration where the control gate wraps around or is positioned above/below floating gate portions. This dimensional transition compensates for reduced planar surface area, maintaining capacitance coupling despite smaller feature sizes.
Solution Approach 2:
The control gate and floating gate structures are nested or interdigitated in a three-dimensional arrangement, maximizing the overlapping surface area between gates within a compact footprint. This nesting approach increases effective coupling area without increasing the device's planar dimensions.
3Productivity
If the distance between adjacent transistors is reduced to increase density, then device integration is improved, but inter-transistor capacitance increases
Solution Approach 1:
The intermediate portion of the floating gate is extracted or removed to create a gap or reduced-cross-section region between adjacent transistor structures. This extraction minimizes the parasitic capacitance coupling between neighboring transistors, allowing closer spacing for higher integration without excessive inter-transistor interference.
Solution Approach 2:
The intermediate portion of the floating gate acts as an intermediary element that can be selectively removed or reduced, serving as a mediator to reduce capacitive coupling between adjacent transistors while maintaining the structural integrity and electrical function of the overall device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains a high coupling ratio even at smaller feature sizes, improving the reliability and performance of semiconductor devices by increasing the capacitance between the floating and control gates while reducing inter-transistor capacitance.
Implementation Method 1
The control gate 12 and the floating gate 14 are capacitively coupled to one another (i.e., positioned such that an electrical capacitance may be generated therebetween)
Implementation Method 2
when a sufficient voltage is applied to the control gate 12, electrons may be caused to 'tunnel' through the tunnel dielectric material 22 from the substrate 11 to the floating gate 14
Data Source
AI summary
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.