Floating Gate With Narrow Tips And Concave Profile For Nonvolatile Memory

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Solution Overview

Problem

Nonvolatile memory devices face challenges in erase efficiency due to unwanted tunneling of charges from the erase gate to the floating gate, which affects device operation, and require an improved design to enhance erase efficiency and reduce cell size.

Innovation Solution

The design incorporates floating gates with narrow tips and concave profiles, along with a wordline having convex profiles, to minimize reverse tunneling and optimize charge transfer during the erase process, while maintaining a compact cell size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a sharp tip is formed at the corner of the floating gate adjacent to the erase gate, then erase efficiency is improved, but unwanted reverse tunneling of charges from the erase gate to the floating gate occurs

Engineering Contradiction:

Improveerase efficiencyVSAvoidreverse tunneling

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The floating gate is designed with non-uniform geometry: sharp tips at corners adjacent to the wordline for efficient charge removal, and a concave profile at the corner adjacent to the erase gate to prevent reverse tunneling. This local differentiation of geometric properties resolves the contradiction by optimizing each region for its specific function.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Instead of forming a sharp tip at the erase gate corner (which would cause reverse tunneling), the invention inverts the approach by creating a concave profile at that specific location. This geometric inversion prevents the harmful effect while maintaining sharp tips at wordline-adjacent corners for efficient erasing.

Inventive Principle:

Principle #13The other way round (Inversion)

2Area of stationary object

If the cell size is reduced, then device integration is improved, but erase efficiency may be compromised

Engineering Contradiction:

Improvecell sizeVSAvoiderase efficiency

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The floating gate geometry is locally optimized with sharp tips positioned precisely at corners adjacent to the wordline, concentrating the erasing action at critical points. This allows effective erasing in a compact cell structure without requiring a larger overall gate area.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves erase efficiency by reducing reverse tunneling and allows for a smaller cell size, enhancing the overall performance of nonvolatile memory devices.

Implementation Method 1

During an erase operation, a voltage may be applied to the erase gate and the charges stored in the floating gate may tunnel to the erase gate

Methodology Applied

Scientific EffectTunneling:

Data Source

PatentUS11721731B2Nonvolatile memory having multiple narrow tips at floating gate

Publication Date: 2023.08.08 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.