Three-Gate Floating-Gate Synapse Array for Compact Analog Neural Weights
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Solution Overview
Problem
Current artificial neural networks face challenges in achieving high-performance information processing due to inadequate hardware technology, specifically high energy inefficiency and bulky synapses in CMOS implementations, which hinder the development of complex neural networks with high connectivity between neurons.
Innovation Solution
A neural network device utilizing a non-volatile memory array with CMOS technology, where each synapse is configured with memory cells having spaced source and drain regions, a floating gate, and control gates, allowing for precise tuning and storage of weight values, enabling efficient and fine-tuned connectivity between neurons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital computing systems (supercomputers, GPUs) with an analog neural network implementation using non-volatile memory cells. The memory cells directly perform analog multiplication and accumulation operations, substituting the mechanical/digital computation process with a physical analog process that consumes less energy while maintaining high computational parallelism
Solution Approach 2:
The patent changes the operational parameters from digital discrete states to analog continuous states. By using floating gate memory cells that can store continuous weight values and perform analog computations, the system achieves both high computational parallelism and improved energy efficiency compared to digital systems
2Use of energy by moving object
If CMOS analog circuits are used for synapses, then energy efficiency is improved, but device area increases due to bulky circuit implementation
Solution Approach 1:
The patent merges the functions of weight storage and computation into a single non-volatile memory cell structure. The floating gate memory cell simultaneously stores the synapse weight and performs the multiplication operation, eliminating the need for separate bulky CMOS analog circuits for weight storage and computation, thereby reducing device area while maintaining energy efficiency
Solution Approach 2:
The non-volatile memory cell serves multiple functions: it stores weight values non-volatently, performs analog multiplication with input signals, and provides high connectivity. This multi-functional approach replaces multiple dedicated CMOS circuits, significantly reducing the overall device area while preserving the energy efficiency benefits of analog computation
3Productivity
If a very large number of synapses are implemented to achieve high connectivity, then computational parallelism is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the neural network into discrete memory cell units that can be systematically arranged in arrays. Each memory cell is a standardized, simple structure that can be replicated and scaled to achieve high connectivity. This segmentation approach allows complex high-connectivity networks to be built from simple, repeatable units, managing hardware complexity while maintaining high computational parallelism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient and precise tuning of synapse weights, reducing energy consumption and increasing computational parallelism, thus addressing the limitations of existing hardware in achieving high-performance neural networks.
Implementation Method 1
Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between
Data Source
AI summary
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.