Floating Gate Fabrication via Selective Nitride Removal
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Solution Overview
Problem
The formation of large topographic steps between flash memory and logic transistor regions in semiconductor fabrication leads to pitting and residue on the logic region during the creation of floating gates in flash memories.
Innovation Solution
A method involving a substrate divided into cell and logic regions, where a silicon oxide and nitride layer cover the regions, with STIs embedded, followed by selective removal of the nitride layer in the cell region to form a recess, and a conductive layer is filled and planarized, then thinned to form a floating gate, while maintaining the nitride layer in the logic region to prevent pitting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the nitride layer is removed in the cell region to form recesses for floating gates, then flash memory fabrication is enabled, but large topographic steps are formed between cell and logic regions causing pitting and residue on the logic region
Solution Approach 1:
The patent applies local quality by making the nitride layer configuration region-specific: the nitride layer is removed in the cell region to enable floating gate formation, while the nitride layer is retained in the logic region to maintain surface flatness and prevent pitting. This selective treatment allows each region to have the properties needed for its specific function without compromising the other region's quality.
2Manufacturing precision
If the conductive layer is planarized using CMP, then surface flatness is improved, but the STIs and nitride layer act as stop layers preventing complete planarization and leaving residual topographic variations
Solution Approach 1:
The patent applies preliminary action by forming the nitride layer in the logic region before the planarization process. This pre-formed layer acts as a protective stop layer that prevents the CMP process from creating pitting and residue in the logic region. By preparing this protective layer in advance, the subsequent planarization can proceed without causing damage to the logic region surface.
Data Source
AI summary
A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.