Floating Gate NVM Low-Moisture Oxide Cap Layer Hydrogen Barrier

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Solution Overview

Problem

Conventional semiconductor fabrication methods fail to adequately suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing, which affects the performance of non-volatile memory (NVM) cells by reducing charge retention and stability.

Innovation Solution

A modified back-end metallization structure is introduced, featuring a cap layer of high-density low-moisture content oxide, such as silane oxide or silicon oxy-nitride, over TEOS-based oxide inter-level dielectric layers to minimize hydrogen generation and migration, thereby enhancing the operating performance of NVM cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If TEOS-based oxide is used for inter-level dielectric layers, then good step coverage and gap filling are achieved, but hydrogen generation and migration occur during aluminum etch processes

Engineering Contradiction:
Improvestep coverageVSAvoidhydrogen generation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A cap layer of high-density low-moisture content oxide is introduced as an intermediary between the TEOS-based oxide ILD layer and the aluminum etch process. This cap layer serves as a barrier that prevents hydrogen generated during aluminum etching from migrating into the underlying ILD and NVM structures, while still allowing the TEOS-based oxide to provide its excellent step coverage and gap filling properties

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric structure is transformed from a single-material TEOS-based oxide layer to a composite structure consisting of multiple layers: the TEOS-based oxide ILD layer providing mechanical support and gap filling, overlaid with a high-density low-moisture content oxide cap layer that provides hydrogen barrier functionality. This composite approach allows each layer to perform its specialized function

Inventive Principle:
Principle #40Composite materials

2Productivity

If conventional back-end processing is used, then manufacturing efficiency is maintained, but charge retention and stability of NVM cells deteriorate

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidcharge retention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cap layer is formed on the ILD layers before the aluminum etch processes occur in the back-end manufacturing sequence. This preliminary protective action ensures that when aluminum etching subsequently takes place, the hydrogen barrier is already in place, preventing hydrogen migration and protecting NVM charge retention without requiring changes to the aluminum deposition or etching processes themselves

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of high-density low-moisture content oxide cap layers significantly reduces hydrogen production and migration, improving data retention and overall performance of NVM cells by isolating the inter-level dielectric material from plasma environments during aluminum etch processes.

Implementation Method 1

The use of high-density low-moisture content oxide cap layers significantly reduces hydrogen production and migration, improving data retention and overall performance of NVM cells by isolating the inter-level dielectric material from plasma environments during aluminum etch processes

Methodology Applied
Scientific EffectPhysical barrier isolation: Physical Containment

Data Source

PatentUS9379194B2Floating gate NVM with low-moisture-content oxide cap layer
Publication Date: 2016.06.28 TOWER SEMICONDUCTOR LTD

AI summary

A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) that is deposited over the ILD layer in lower metallization layers to serve as an etch-stop for the subsequently-formed metal layer, and to isolate the ILD material from the plasma environment during aluminum over etch, which significantly reduces the production and migration of hydrogen that diminishes charge storage by the floating gates.