Floating Gate Non-Volatile Memory With Variable Capacitive Coupling

The patent merges the floating gate function with existing CMOS transistor structures by electrically coupling the floating gate to the drain region of an NMOS transistor. This integration eliminates the need for separate interconnect layers to access the floating gate, as the drain region serves dual purposes: as a control terminal for the transistor and as an electrical coupling path to the floating gate for programming operations.

The patent inverts the conventional OTP approach by using NMOS instead of PMOS and programming from conducting to non-conducting state rather than the reverse. This inversion eliminates the need for additional masking steps because the NMOS device naturally conducts in the unprogrammed state, and programming simply involves removing carriers to achieve the non-conducting programmed state, which is the desired final state for OTP applications.

The patent employs channel hot hole injection programming in NMOS devices, which is a self-limiting process. The programming mechanism automatically regulates energy consumption because the hot hole injection process naturally ceases when the floating gate reaches a sufficient positive potential, preventing excessive energy usage. The device structure and programming mechanism work together to self-regulate the energy input required for successful programming.

The patent enables multi-level functionality by dynamically controlling the programming voltage applied to the drain region. By varying the magnitude and duration of the programming voltage, different amounts of charge are injected into the floating gate, creating distinct threshold voltage levels that represent multiple data states. This dynamic voltage control approach allows a single memory cell to store multiple bits of information without requiring additional physical structures or complex processing steps.