Floating Gate Overlap Consistency in Nonvolatile Memory
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Solution Overview
Problem
Misalignment between floating gates and active regions in 2-cells-per-bit nonvolatile memory structures leads to significant differences in coupling ratios, affecting erase speed due to varying overlapping areas between floating gates and erase lines.
Innovation Solution
Incorporating additional oxide-defined (OD) regions that protrude vertically and are partially overlapped with floating gates, these regions are capacitively coupled to the erase region, helping to reduce coupling ratio differences by adjusting the overlap areas between floating gates and erase lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 2-cells-per-bit nonvolatile memory structure is used, then data retention capability is improved, but coupling ratio difference increases due to misalignment between floating gates and active regions
Solution Approach 1:
The patent introduces addition regions with different properties (heavier doping concentration) in specific locations of the OD region to compensate for misalignment effects. By creating local quality differences through selective doping, the coupling ratio is adjusted locally to reduce variations caused by floating gate misalignment, thus improving manufacturing precision without compromising data retention capability.
Solution Approach 2:
The patent changes the doping concentration parameter in specific regions (addition regions) to adjust the electrical characteristics. By increasing the doping concentration in the addition regions compared to the original OD region, the patent modifies the local electrical field distribution and capacitance characteristics, thereby compensating for coupling ratio differences caused by misalignment.
2Ease of manufacture
If misalignment occurs between floating gates and active regions, then device fabrication becomes simpler, but overlapping areas between floating gates and erase line become significantly different
Solution Approach 1:
The addition regions are strategically positioned and doped with higher concentration to locally enhance the electrical interaction. This local quality modification compensates for the reduced overlapping area in misaligned configurations, ensuring that even with fabrication tolerances, the effective coupling area remains consistent across different cells.
Solution Approach 2:
The patent addresses the two-dimensional misalignment problem by introducing a doping concentration dimension. Instead of trying to control the geometric overlap area precisely, the patent uses doping concentration as an additional degree of freedom to adjust and equalize the effective coupling, transforming a geometric control problem into an electrical property adjustment problem.
3Manufacturing precision
If addition regions are added to OD region, then coupling ratio difference is reduced, but device structure becomes more complex
Solution Approach 1:
The addition regions are merged with the existing OD region structure rather than being completely separate components. The doping process integrates the addition regions into the substrate, combining the compensation function with the existing isolation structure, thus reducing overall device complexity while maintaining coupling ratio consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively minimizes the difference in coupling ratios, thereby improving the consistency and efficiency of the erase process in nonvolatile memory structures.
Implementation Method 1
the floating gate has an extended portion capacitively coupled to the erase region
Data Source
AI summary
A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.