Floating Gate Overlap Optimization for Weak-Program Memory
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Solution Overview
Problem
Non-volatile memory devices often experience inefficiencies in program operations due to weak-program or stuck bit issues, resulting from improper electron injection during manufacturing, which affects the efficiency of data storage and retrieval.
Innovation Solution
The memory device design includes a substrate with a channel region, doped regions, a floating gate, and a dielectric layer, where the overlap area between the floating gate and the source or drain is optimized, and the distance between the floating gate and the other doped region is adjusted to enhance electron injection, thereby improving weak-program and stuck bit conditions during program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the initial electron injection point is too high during manufacturing, then electron injection efficiency is reduced, but weak-program occurs during program operation
Solution Approach 1:
The patent adjusts the overlap area between the floating gate and doped regions as a geometric parameter to modify the electric field distribution and electron injection characteristics. By changing the overlap width from conventional designs to optimized values, the initial electron injection point is lowered to improve both manufacturing precision and program operation reliability
Solution Approach 2:
The patent creates asymmetric overlap configurations where the floating gate overlaps differently with the source and drain doped regions. This local quality variation allows selective enhancement of electron injection at specific locations, addressing the weak-program issue by optimizing the injection point position in the channel region
2Productivity
If electrons are not injected effectively during manufacturing, then program operation efficiency is reduced, but stuck bit occurs
Solution Approach 1:
The patent modifies the geometric parameters of the floating gate and doped regions to enhance the coupling effect and electric field strength during electron injection. By optimizing the overlap area and separation distance, effective electron injection is achieved, improving program operation efficiency while preventing stuck bit through reliable bit flipping
Solution Approach 2:
The patent designs the floating gate structure with pre-optimized overlap characteristics before operation. This preliminary structural configuration ensures that during program operation, electrons are injected effectively from the outset, preventing stuck bit conditions before they can occur
3Reliability
If the overlap area between floating gate and doped regions is increased, then coupling effect is enhanced, but device area increases
Solution Approach 1:
The patent implements asymmetric overlap where the floating gate overlaps more significantly with one doped region than the other. This localized enhancement of coupling effect in specific areas achieves improved electron injection and reliability without requiring uniform increase in overlap throughout the entire device, thus controlling the overall device area
Solution Approach 2:
The patent optimizes the vertical stacking and lateral positioning of the floating gate relative to doped regions, utilizing three-dimensional spatial arrangement to maximize coupling effect within a constrained planar footprint. By adjusting the overlap in multiple dimensions, strong coupling is achieved without proportional increase in device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized design increases the coupling effect between the floating gate and the doped regions, leading to improved electron injection and enhanced program operation efficiency, with nearly 33% improvement in discharge current and reduced leakage current, effectively addressing weak-program and stuck bit issues.
Implementation Method 1
the efficiency of the program operation of the non-volatile memory may be depended on the coupling effect between the gate and the source and the coupling effect between the gate and the drain
Data Source
AI summary
Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.