Floating-Gate Memory Cell Layout for Oxide Reliability
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in reliability due to damage to the tunneling oxide layer during programming and erase operations, and the stacked gate structure makes it difficult to integrate with logic devices without compromising electrical performance.
Innovation Solution
A non-volatile memory device with a reduced height is designed, featuring a trench in the substrate with an erase gate having a concave corner, a control gate with a bottom surface higher than the erase gate, and a floating gate with a lower tip extending beyond the trench sidewall, which enhances electron extraction efficiency and reduces electrical coupling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure including select gate and erase gate is adopted, then the memory device can perform programming and erase operations, but the memory device becomes taller and difficult to integrate with logic devices
Solution Approach 1:
The invention transitions from a vertical stacked gate structure to a lateral arrangement where the erase gate is positioned beside the control gate in the same plane. This dimensional change allows the memory device to maintain its operational capabilities while reducing the vertical height, enabling better integration with logic devices that have planar gate structures.
Solution Approach 2:
The gate structure is segmented into a control gate and an erase gate that are spatially separated and positioned at different locations relative to the floating gate. The control gate is disposed over the channel region while the erase gate is positioned beside it, allowing independent operation and reducing the need for vertical stacking.
2Length of moving object
If the ILD layer above the memory device is made thinner to miniaturize contact plugs, then contact plug line widths can be reduced, but electrical coupling between the memory device and interconnects increases
Solution Approach 1:
The invention introduces an intermediate region where the erase gate is positioned beside the control gate, creating a spatial buffer zone. This intermediate positioning allows the ILD layer to maintain adequate thickness above the memory device structure, preventing direct electrical coupling between the memory device and upper interconnects while still enabling miniaturized contact plugs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves the reliability of the memory device by reducing stress on the tunneling oxide layer and minimizing electrical coupling, allowing for more efficient integration with logic devices while maintaining high operational performance.
Implementation Method 1
electrons have to be injected into or pulled out of the floating gate through a tunneling oxide layer disposed under the floating gate
Implementation Method 2
a suitable voltage is respectively applied to the source region, the drain region, and the control gate, such that electrons are injected into a floating gate, or electrons are pulled out from the floating gate
Data Source
AI summary
A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is disposed in the substrate. The erase gate is disposed in the trench and includes a concave corner. The control gate is disposed on the substrate, and a bottom surface of the control gate is higher than a bottom surface of the erase gate. The floating gate is disposed on the substrate, and the floating gate includes a lower tip pointing toward the concave corner of the erase gate and extending beyond a sidewall of the trench.