Floating Gate Memory Isolation Sequence for Uniform Tunneling Oxide
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving reliability and operation speed, particularly due to non-uniform thickness of the tunneling dielectric layer leading to corner thinning issues.
Innovation Solution
The manufacturing method involves forming the floating gate layer and tunneling dielectric layer before the second isolation structure in the memory region, ensuring a uniform thickness of the tunneling dielectric layer and allowing for adjustable thickness adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the tunneling dielectric layer is formed after the second isolation structure, then the manufacturing process follows conventional sequence, but corner thinning occurs and thickness uniformity deteriorates
Solution Approach 1:
The tunneling dielectric layer is formed in advance before the second isolation structure is created. This preliminary action prevents corner thinning by establishing the dielectric layer when the substrate surface is still accessible and uniform, avoiding subsequent thickness non-uniformity issues that would occur if formed after isolation structures are in place.
2Reliability
If the tunneling dielectric layer thickness is fixed by conventional processes, then manufacturing is simpler, but operation speed and reliability cannot be optimized
Solution Approach 1:
The thickness of the tunneling dielectric layer is made adjustable through process parameter optimization. By controlling deposition conditions and timing, the thickness can be precisely tuned to achieve optimal balance between reliability (preventing corner thinning) and performance (improving operation speed), while maintaining manufacturing feasibility.
Data Source
AI summary
A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. The substrate includes a peripheral region and a memory region. A first isolation structure is formed in the substrate in the peripheral region. After the first isolation structure is formed, a first floating gate layer and a tunneling dielectric layer are formed in the memory region. The first floating gate layer is located on the substrate. The tunneling dielectric layer is located between the first floating gate layer and the substrate. After the first floating gate layer and the tunneling dielectric layer are formed, a second isolation structure is formed in the substrate in the memory region.