Nonvolatile Memory Floating Gate Protective Layer and Air Gap
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Solution Overview
Problem
Conventional nonvolatile memory devices experience increased distribution differences and interference between memory cells due to impurity loss and ion implantation during manufacturing processes, leading to non-uniform memory cell characteristics as integration density increases.
Innovation Solution
The implementation of a nonvolatile memory device with gate structures including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate, where a protective layer with low adhesive strength is formed on the sidewalls of the floating gate to prevent impurity transfer and an air gap is created between gate structures to reduce interference, using a method that involves sequential layer formation and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures are formed with polysilicon floating gate doped with impurities, then the floating gate can store charge, but impurities escape during heat treatment or ion implantation occurs during subsequent processes, causing non-uniform memory cell characteristics
Solution Approach 1:
A protective layer is introduced as an intermediary between the floating gate and the external environment. This protective layer prevents direct interaction between the polysilicon floating gate and impurities during subsequent heat treatment or ion implantation processes, thereby maintaining impurity concentration stability and ensuring uniform memory cell characteristics.
Solution Approach 2:
The protective layer is formed in advance before subsequent heat treatment or ion implantation processes. This preliminary protective action prevents impurity escape during heat treatment and blocks external impurity entry during ion implantation, counteracting potential harmful effects before they can occur.
2Productivity
If the distance between gate structures is decreased to increase integration degree, then device integration density increases, but interference between memory cells increases
Solution Approach 1:
An air gap is introduced as a physical intermediary between adjacent gate structures. This air gap acts as an isolation medium that reduces capacitive coupling and interference between memory cells, enabling higher integration density without proportionally increasing cell-to-cell interference.
Solution Approach 2:
Instead of increasing horizontal spacing between gate structures (which would reduce integration density), the solution introduces a vertical dimension feature - the air gap - that provides isolation in the vertical field while maintaining horizontal compactness. This dimensional approach allows high integration density with reduced interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces distribution differences and interference between memory cells by maintaining impurity integrity and increasing the size of air gaps between floating gates, thereby enhancing memory cell uniformity and reducing cell-to-cell interference.
Implementation Method 1
a protective layer formed on sidewalls of the floating gate configured to block impurities from being transferred from or to the floating gate
Implementation Method 2
a second insulating layer covering the gate structures and having an air gap formed between the gate structures
Data Source
AI summary
A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.