Floating Gate Transistor PUF with Asymmetric Threshold Distribution
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Solution Overview
Problem
Existing physically unclonable function (PUF) structures using floating gate transistors face challenges in maintaining robustness against external variations and aging while being difficult to extract, with traditional techniques increasing data retention and readability also making data extraction easier.
Innovation Solution
A set of pairs of floating gate transistors with threshold voltages belonging to a common random distribution, where differential reading identifies unreliable pairs and controlled shifting of threshold voltages ensures the difference remains within the distribution, making the function physically unclonable and resistant to extraction by microscopy techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional techniques are used to increase data retention and readability in floating-gate transistors, then data retention and discrimination capacity are improved, but data extraction becomes easier
Solution Approach 1:
The patent applies asymmetry by creating two distinct threshold voltage distributions (D0 and D1) that are separated by a margin, making the stored data asymmetrical and unreadable by symmetric scanning microscopy techniques. The differential reading means measures the difference between transistors with different threshold voltage distributions, creating an asymmetrical measurement approach that prevents extraction while maintaining readability.
Solution Approach 2:
The patent changes the parameter of threshold voltage distribution by ensuring that transistors belong to one of two well-separated distributions rather than a single distribution. This parameter change creates a margin-based separation that improves data retention while simultaneously preventing extraction, as the scanning microscopy techniques cannot distinguish between transistors from different distributions when the margin is sufficient.
2Reliability
If floating-gate transistors are used for physically non-clonable functions, then data retention and robustness are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies self-service by utilizing the natural random variations in threshold voltage that occur during standard CMOS manufacturing processes. Instead of adding dedicated manufacturing steps to create physical unclonability, the invention leverages the inherent randomness already present in floating-gate transistor fabrication, allowing the system to serve itself in generating unique identifiers without additional manufacturing complexity.
Solution Approach 2:
The patent makes floating-gate transistors serve multiple functions: they provide data storage with excellent retention capabilities while simultaneously generating physically unclonable identifiers. The same floating-gate transistor structure used for robust data retention also serves as the source of random variations for PUF functionality, eliminating the need for separate structures and reducing overall manufacturing complexity.
3Measurement precision
If threshold voltage levels are separated into distinct distributions for reading, then data readability is improved, but extraction by microscopy becomes easier
Solution Approach 1:
The patent transitions from a single-dimension threshold voltage separation to a two-dimensional approach by considering both the threshold voltage value and the distribution membership. The differential reading means measures the difference between transistors, adding a dimensional aspect to the measurement that improves readability while the margin-based separation in the threshold voltage domain prevents microscopy extraction by making the transistors appear indistinguishable in the physical domain.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides robust data storage with excellent retention capabilities, ensuring the function's unclonability and resistance to extraction, while being easy to produce using existing technologies, maintaining viability and distinction between threshold voltages.
Implementation Method 1
data is represented by threshold voltage levels Vt of floating-gate transistors. These threshold voltage levels are imposed by injecting positive or negative charges into the floating gates
Implementation Method 2
a differential reading means configured to measure the difference between the effective threshold voltages of the pairs of floating-gate transistors
Implementation Method 3
a writing means configured to shift the effective threshold voltage of one floating-gate transistor of each unreliable pair, in a controlled and limited manner
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
The physically non-clonable function device (DIS) comprises a set (ENS) of pairs (P) of floating-gate transistors (FGT1, FGT2) intended to have the same threshold voltage but each having an effective threshold voltage (Vteff) belonging to a common random distribution (DST), a differential reading means (LECT) configured to measure the difference between the effective threshold voltages (Vteff) of the pairs (P) of floating-gate transistors (FGT1, FGT2) and to identify pairs of floating-gate transistors called unreliable (NF) whose difference between the effective threshold voltages is less than a margin value (MRG), and a writing means (ECR) configured to shift the effective threshold voltage (C, E) of one floating-gate transistor of each unreliable (NF) pair, in a controlled and limited manner so that the shifted threshold voltage remains within said common random distribution (DST).