Floating Gate Memory Cell Recess Channel Integration
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Solution Overview
Problem
The integration of 1.5 T ESF3 memory devices is complicated due to the higher stack topology of gate structures, leading to damage during polish operations, which increases costs with additional processes and masks required to mitigate damage.
Innovation Solution
Incorporating a recess channel in each floating gate memory cell and using a common source coupling source side injection programming method without control gates, reducing the structure topology and enhancing coupling ratios, thus simplifying integration and reducing the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a higher stack topology of gate structures is used in 1.5 T ESF3 memory devices, then memory array density is increased, but damage during polish operations occurs and manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the control gate structure from the memory cell, transitioning from a split-gate architecture to a control-gateless architecture. This extraction eliminates the higher stack topology that caused polish damage and integration complexity, while preserving the floating gate structure that enables high-density storage.
Solution Approach 2:
The patent segments the gate functionality by separating the control gate from the floating gate structure. The floating gate retains its charge storage function while the control gate is removed, allowing independent optimization of each component's role and reducing overall structural complexity.
2Reliability
If additional processes and masks are used to mitigate polish damage, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent performs preliminary action by removing the control gate structure before the polish operation occurs. This preventive measure eliminates the root cause of polish damage rather than requiring additional protective processes or masks, thereby maintaining reliability while reducing manufacturing complexity and cost.
3Ease of operation
If control gates are included in floating gate memory cells, then programming control is improved, but structure topology increases and short channel effect worsens
Solution Approach 1:
The control gate is extracted from the memory cell structure, eliminating the higher stack topology. The floating gate memory cell operates without a control gate, using alternative mechanisms for charge injection and control, thereby reducing structural complexity and mitigating the short channel effect while maintaining programming functionality.
Solution Approach 2:
The patent transitions to a control-gateless architecture that operates in a different dimensional configuration. By removing the vertical stack of control gate plus floating gate, the structure achieves a lower topology that reduces the short channel effect, while programming control is achieved through alternative charge injection methods from the bit line and word line.
Data Source
AI summary
A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.